From patchwork Thu Jul 28 09:28:04 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: YT Shen X-Patchwork-Id: 9250995 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 67CCD6077C for ; Thu, 28 Jul 2016 09:33:10 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5808F26D08 for ; Thu, 28 Jul 2016 09:33:10 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4C12E26E54; Thu, 28 Jul 2016 09:33:10 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, UNPARSEABLE_RELAY autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E2E2926D08 for ; Thu, 28 Jul 2016 09:33:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2452B6E7A6; Thu, 28 Jul 2016 09:33:05 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mailgw01.mediatek.com (unknown [210.61.82.183]) by gabe.freedesktop.org (Postfix) with ESMTP id 522DE6E7AC for ; Thu, 28 Jul 2016 09:30:38 +0000 (UTC) Received: from mtkhts09.mediatek.inc [(172.21.101.70)] by mailgw01.mediatek.com (envelope-from ) (mhqrelay.mediatek.com ESMTP with TLS) with ESMTP id 27532082; Thu, 28 Jul 2016 17:30:36 +0800 Received: from mtkslt301.mediatek.inc (10.21.14.114) by mtkhts09.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 14.3.266.1; Thu, 28 Jul 2016 17:30:33 +0800 From: YT Shen To: , Philipp Zabel Subject: [PATCH v5 10/10] arm: dts: mt2701: Add display subsystem related nodes for MT2701 Date: Thu, 28 Jul 2016 17:28:04 +0800 Message-ID: <1469698084-20185-11-git-send-email-yt.shen@mediatek.com> X-Mailer: git-send-email 1.7.9.5 In-Reply-To: <1469698084-20185-1-git-send-email-yt.shen@mediatek.com> References: <1469698084-20185-1-git-send-email-yt.shen@mediatek.com> MIME-Version: 1.0 X-MTK: N Cc: Mark Rutland , devicetree@vger.kernel.org, Russell King , srv_heupstream@mediatek.com, Pawel Moll , Ian Campbell , emil.l.velikov@gmail.com, linux-kernel@vger.kernel.org, Mao Huang , Rob Herring , linux-mediatek@lists.infradead.org, Kumar Gala , Matthias Brugger , yingjoe.chen@mediatek.com, Sascha Hauer , linux-arm-kernel@lists.infradead.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP This patch adds the device nodes for the DISP function blocks for MT2701 Signed-off-by: YT Shen --- arch/arm/boot/dts/mt2701.dtsi | 100 +++++++++++++++++++++++++++++++++++++++++ 1 file changed, 100 insertions(+) diff --git a/arch/arm/boot/dts/mt2701.dtsi b/arch/arm/boot/dts/mt2701.dtsi index 363de0d..7da9310 100644 --- a/arch/arm/boot/dts/mt2701.dtsi +++ b/arch/arm/boot/dts/mt2701.dtsi @@ -24,6 +24,11 @@ compatible = "mediatek,mt2701"; interrupt-parent = <&sysirq>; + aliases { + rdma0 = &rdma0; + rdma1 = &rdma1; + }; + cpus { #address-cells = <1>; #size-cells = <0>; @@ -171,6 +176,16 @@ power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; }; + mipi_tx0: mipi-dphy@10010000 { + compatible = "mediatek,mt2701-mipi-tx"; + reg = <0 0x10010000 0 0x90>; + clocks = <&clk26m>; + clock-output-names = "mipi_tx0_pll"; + #clock-cells = <0>; + #phy-cells = <0>; + status = "disabled"; + }; + sysirq: interrupt-controller@10200100 { compatible = "mediatek,mt2701-sysirq", "mediatek,mt6577-sysirq"; @@ -255,6 +270,68 @@ status = "disabled"; }; + ovl@14007000 { + compatible = "mediatek,mt2701-disp-ovl"; + reg = <0 0x14007000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_OVL>; + iommus = <&iommu MT2701_M4U_PORT_DISP_OVL_0>; + mediatek,larb = <&larb0>; + }; + + rdma0: rdma@14008000 { + compatible = "mediatek,mt2701-disp-rdma"; + reg = <0 0x14008000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_RDMA>; + iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA>; + mediatek,larb = <&larb0>; + }; + + wdma@14009000 { + compatible = "mediatek,mt2701-disp-wdma"; + reg = <0 0x14009000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_WDMA>; + iommus = <&iommu MT2701_M4U_PORT_DISP_WDMA>; + mediatek,larb = <&larb0>; + }; + + bls@1400a000 { + compatible = "mediatek,mt2701-disp-pwm"; + reg = <0 0x1400a000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_BLS>; + }; + + color@1400b000 { + compatible = "mediatek,mt2701-disp-color"; + reg = <0 0x1400b000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_COLOR>; + }; + + dsi0: dsi@1400c000 { + compatible = "mediatek,mt2701-dsi"; + reg = <0 0x1400c000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DSI_ENGINE>, <&mmsys CLK_MM_DSI_DIG>, + <&mipi_tx0>; + clock-names = "engine", "digital", "hs"; + mediatek,syscon-dsi = <&mmsys 0x138>; + mediatek,ssc-range = <5>; + phys = <&mipi_tx0>; + phy-names = "dphy"; + status = "disabled"; + }; + + mutex: mutex@1400e000 { + compatible = "mediatek,mt2701-disp-mutex"; + reg = <0 0x1400e000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_MUTEX_32K>; + }; + larb0: larb@14010000 { compatible = "mediatek,mt2701-smi-larb"; reg = <0 0x14010000 0 0x1000>; @@ -265,6 +342,29 @@ power-domains = <&scpsys MT2701_POWER_DOMAIN_DISP>; }; + rdma1: rdma@14012000 { + compatible = "mediatek,mt2701-disp-rdma"; + reg = <0 0x14012000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DISP_RDMA1>; + iommus = <&iommu MT2701_M4U_PORT_DISP_RDMA1>; + mediatek,larb = <&larb0>; + }; + + dpi0: dpi@14014000 { + compatible = "mediatek,mt2701-dpi"; + reg = <0 0x14014000 0 0x1000>; + interrupts = ; + clocks = <&mmsys CLK_MM_DPI1_DIGL>, + <&mmsys CLK_MM_DPI1_ENGINE>, + <&topckgen CLK_TOP_DPI1_SEL>, + <&topckgen CLK_TOP_TVDPLL>, + <&topckgen CLK_TOP_TVDPLL_D2>, + <&topckgen CLK_TOP_TVDPLL_D4>; + clock-names = "pixel", "engine", "sel","div1","div2","div4"; + status = "disabled"; + }; + imgsys: syscon@15000000 { compatible = "mediatek,mt2701-imgsys", "syscon"; reg = <0 0x15000000 0 0x1000>;