| Message ID | 1470945277-7973-2-git-send-email-cpaul@redhat.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Thu, Aug 11, 2016 at 03:54:30PM -0400, Lyude wrote: > In order to add proper support for the SAGV, we need to be able to know > what the cause of a failure to change the SAGV through the pcode mailbox > was. The reasoning for this is that some very early pre-release Skylake > machines don't actually allow you to control the SAGV on them, and > indicate an invalid mailbox command was sent. > > This also might come in handy in the future for debugging. > > Signed-off-by: Lyude <cpaul@redhat.com> > Cc: Matt Roper <matthew.d.roper@intel.com> > Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> > Cc: Daniel Vetter <daniel.vetter@ffwll.ch> > Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> > Cc: stable@vger.kernel.org > --- > drivers/gpu/drm/i915/i915_reg.h | 1 + > drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++++ > 2 files changed, 11 insertions(+) > > diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h > index da82744..73b3d4d 100644 > --- a/drivers/gpu/drm/i915/i915_reg.h > +++ b/drivers/gpu/drm/i915/i915_reg.h > @@ -7121,6 +7121,7 @@ enum { > #define VLV_MEDIA_C0_COUNT _MMIO(0x13811C) > > #define GEN6_PCODE_MAILBOX _MMIO(0x138124) > +#define GEN6_PCODE_INVALID_CMD (1<<0) It doesn't work quite like that. Instead the low 8 bits will contian the error code, iff pcode has cleared the "READY" bit: snb-ivb docs say: 00h MAILBOX_GTDRIVER_CC_SUCCESS 01h MAILBOX_GTDRIVER_CC_ILLEGAL_CMD 02h MAILBOX_GTDRIVER_CC_MIN_FREQUENCY_TABLE_GT_RATIO_OUT_OF_RANGE 03h MAILBOX_GTDRIVER_CC_TIMEOUT FFh MAILBOX_GTDRIVER_CC_UNIMPLEMENTED_CMD hsw-bdw docs say: 00h SUCCESS 01h ILLEGAL_CMD 02h TIMEOUT 03h ILLEGAL_DATA 10h MIN_FREQUENCY_TABLE_GT_RATIO_OUT_OF_RANGE skl docs say: 00h SUCCESS 01h ILLEGAL_CMD 02h TIMEOUT 03h ILLEGAL_DATA So looks like 02h and 03h will need to be interpreted in two different ways depending on the platform. Assuming we want to decode the error into a a human readable form for dmesg. > #define GEN6_PCODE_READY (1<<31) > #define GEN6_PCODE_WRITE_RC6VIDS 0x4 > #define GEN6_PCODE_READ_RC6VIDS 0x5 > diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c > index 99014d7..8752730 100644 > --- a/drivers/gpu/drm/i915/intel_pm.c > +++ b/drivers/gpu/drm/i915/intel_pm.c > @@ -7674,6 +7674,11 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val > *val = I915_READ_FW(GEN6_PCODE_DATA); > I915_WRITE_FW(GEN6_PCODE_DATA, 0); > > + if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_INVALID_CMD) { > + DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access indicated invalid command\n"); > + return -EINVAL; > + } > + > return 0; > } > > @@ -7704,6 +7709,11 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, > > I915_WRITE_FW(GEN6_PCODE_DATA, 0); > > + if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_INVALID_CMD) { > + DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access indicated invalid command\n"); > + return -EINVAL; > + } > + > return 0; > } > > -- > 2.7.4
diff --git a/drivers/gpu/drm/i915/i915_reg.h b/drivers/gpu/drm/i915/i915_reg.h index da82744..73b3d4d 100644 --- a/drivers/gpu/drm/i915/i915_reg.h +++ b/drivers/gpu/drm/i915/i915_reg.h @@ -7121,6 +7121,7 @@ enum { #define VLV_MEDIA_C0_COUNT _MMIO(0x13811C) #define GEN6_PCODE_MAILBOX _MMIO(0x138124) +#define GEN6_PCODE_INVALID_CMD (1<<0) #define GEN6_PCODE_READY (1<<31) #define GEN6_PCODE_WRITE_RC6VIDS 0x4 #define GEN6_PCODE_READ_RC6VIDS 0x5 diff --git a/drivers/gpu/drm/i915/intel_pm.c b/drivers/gpu/drm/i915/intel_pm.c index 99014d7..8752730 100644 --- a/drivers/gpu/drm/i915/intel_pm.c +++ b/drivers/gpu/drm/i915/intel_pm.c @@ -7674,6 +7674,11 @@ int sandybridge_pcode_read(struct drm_i915_private *dev_priv, u32 mbox, u32 *val *val = I915_READ_FW(GEN6_PCODE_DATA); I915_WRITE_FW(GEN6_PCODE_DATA, 0); + if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_INVALID_CMD) { + DRM_DEBUG_DRIVER("warning: pcode (read) mailbox access indicated invalid command\n"); + return -EINVAL; + } + return 0; } @@ -7704,6 +7709,11 @@ int sandybridge_pcode_write(struct drm_i915_private *dev_priv, I915_WRITE_FW(GEN6_PCODE_DATA, 0); + if (I915_READ_FW(GEN6_PCODE_MAILBOX) & GEN6_PCODE_INVALID_CMD) { + DRM_DEBUG_DRIVER("warning: pcode (write) mailbox access indicated invalid command\n"); + return -EINVAL; + } + return 0; }
In order to add proper support for the SAGV, we need to be able to know what the cause of a failure to change the SAGV through the pcode mailbox was. The reasoning for this is that some very early pre-release Skylake machines don't actually allow you to control the SAGV on them, and indicate an invalid mailbox command was sent. This also might come in handy in the future for debugging. Signed-off-by: Lyude <cpaul@redhat.com> Cc: Matt Roper <matthew.d.roper@intel.com> Cc: Maarten Lankhorst <maarten.lankhorst@linux.intel.com> Cc: Daniel Vetter <daniel.vetter@ffwll.ch> Cc: Ville Syrjälä <ville.syrjala@linux.intel.com> Cc: stable@vger.kernel.org --- drivers/gpu/drm/i915/i915_reg.h | 1 + drivers/gpu/drm/i915/intel_pm.c | 10 ++++++++++ 2 files changed, 11 insertions(+)