From patchwork Mon Oct 17 16:30:48 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Bartosz Golaszewski X-Patchwork-Id: 9379865 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 5AE9E607D4 for ; Mon, 17 Oct 2016 16:31:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 4C13028E99 for ; Mon, 17 Oct 2016 16:31:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 40CBD28F05; Mon, 17 Oct 2016 16:31:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BD81728E99 for ; Mon, 17 Oct 2016 16:31:19 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 790266E563; Mon, 17 Oct 2016 16:31:13 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-vk0-x22f.google.com (mail-vk0-x22f.google.com [IPv6:2607:f8b0:400c:c05::22f]) by gabe.freedesktop.org (Postfix) with ESMTPS id 61E646E55F for ; Mon, 17 Oct 2016 16:31:08 +0000 (UTC) Received: by mail-vk0-x22f.google.com with SMTP id 2so183164855vkb.3 for ; Mon, 17 Oct 2016 09:31:08 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=baylibre-com.20150623.gappssmtp.com; s=20150623; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=SSfdvQnTE3/O6cchEUUspDbOxuuLrr2ZV0xK0M5ORf8=; b=L0ji5KFKV5AyVogjoEtnHTRFHxkztwPVj6QLvD6bvUeK5YUlPGPN5nUmKqr2kHOKou ZUBkeFaNgJKTCMUbEpq1jDHveKyJZJ6jmCkBqii95EZj6fy7MiGb8swLa3OVIM53or/l 1Z+RmHjM+dERwIWjeyCXcngEJGlQHFY5PbgZDkK954qYjVfOcBJbw/8FcDzdDBTwK1Pi GH3rQpHDsRYqbSpn4GUO0dlNS3SaQhGjQD2fVIujIv34/mIk2dKRNybfZzDFP7++nQOK /ALFypL+N6MPS4vsSHCKQO4J9RwHELTDNejv7r1SbbhRSi8qU6tTK9vnju3S3AAHrhDj 0JpA== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20130820; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=SSfdvQnTE3/O6cchEUUspDbOxuuLrr2ZV0xK0M5ORf8=; b=HqkKS/OdYJ6XFH5/t0ta7K/ryfasu8MYsQTgtxgRabuJFcZ+EfIVUo+uA22TxOvDL8 ubp8nuIcldxgWAxFW0T6BrcBgnGh0ReL0zQDel91hE05HyNa1lvAOPo/8MkibBeaPjii jJ0ddHH2DkM+zVd0+AXTE2cnypYwxI31TxEt66fVWQjzuAgBwLRBtAkjedshzETeHYSR G0pnHPhqeC1vlzqOid5njhODnvq4ACYON1VdaTKLHHM9b2gjreL0iXIiDFSuWoBPBBPI t2v67khAw3vn0GKSp9jgJS0JtQ3CC0bj9qCNpGkMdBtWaXE9Ho7aLH7zizkJ2wlHluKG 9G4g== X-Gm-Message-State: AA6/9RlQ4cK/aWDbG+mCTYqhFhpiNkWS7epcDLOXvcg+KkOSzTjnIoRoc85/3ghj4UiLXY4Z X-Received: by 10.194.238.162 with SMTP id vl2mr11597089wjc.39.1476721867313; Mon, 17 Oct 2016 09:31:07 -0700 (PDT) Received: from localhost.localdomain (static-46-238-241-125.awacom.net. [46.238.241.125]) by smtp.gmail.com with ESMTPSA id j1sm43945514wjl.21.2016.10.17.09.31.05 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 17 Oct 2016 09:31:06 -0700 (PDT) From: Bartosz Golaszewski To: Kevin Hilman , Michael Turquette , Sekhar Nori , Rob Herring , Frank Rowand , Mark Rutland , Peter Ujfalusi , Russell King Subject: [PATCH 1/3] ARM: memory: da8xx-ddrctl: new driver Date: Mon, 17 Oct 2016 18:30:48 +0200 Message-Id: <1476721850-454-2-git-send-email-bgolaszewski@baylibre.com> X-Mailer: git-send-email 2.1.4 In-Reply-To: <1476721850-454-1-git-send-email-bgolaszewski@baylibre.com> References: <1476721850-454-1-git-send-email-bgolaszewski@baylibre.com> Cc: linux-devicetree , LKML , linux-drm , Bartosz Golaszewski , Tomi Valkeinen , Jyri Sarha , arm-soc , Laurent Pinchart X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Create a new driver for the da8xx DDR2/mDDR controller and implement support for writing to the Peripheral Bus Burst Priority Register. Signed-off-by: Bartosz Golaszewski --- .../memory-controllers/ti-da8xx-ddrctl.txt | 25 +++++++ drivers/memory/Kconfig | 8 +++ drivers/memory/Makefile | 1 + drivers/memory/da8xx-ddrctl.c | 77 ++++++++++++++++++++++ 4 files changed, 111 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt create mode 100644 drivers/memory/da8xx-ddrctl.c diff --git a/Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt b/Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt new file mode 100644 index 0000000..e340404 --- /dev/null +++ b/Documentation/devicetree/bindings/memory-controllers/ti-da8xx-ddrctl.txt @@ -0,0 +1,25 @@ +* Device tree bindings for Texas Instruments da8xx DDR2/mDDR memory controller + +The DDR2/mDDR memory controller present on Texas Instruments da8xx SoCs memory +maps a set of registers which allow to tweak the controller's behavior. + +Documentation: +OMAP-L138 (DA850) - http://www.ti.com/lit/ug/spruh82c/spruh82c.pdf + +Required properties: + +- compatible: "ti,da850-ddrctl" + +Optional properties: + +- ti,pr-old-count: Priority raise old counter. Specifies the number of + memory transfers after which the DDR2/mDDR memory + controller will elevate the priority of the oldest + command in the command FIFO. Must be between 0-255. + +Example for da850 shown below. + +ddrctl { + compatible = "ti,da850-ddrctl"; + ti,pr-old-count = <0x20>; +}; diff --git a/drivers/memory/Kconfig b/drivers/memory/Kconfig index 4b4c0c3..ec80e35 100644 --- a/drivers/memory/Kconfig +++ b/drivers/memory/Kconfig @@ -134,6 +134,14 @@ config MTK_SMI mainly help enable/disable iommu and control the power domain and clocks for each local arbiter. +config DA8XX_DDRCTL + bool "Texas Instruments da8xx DDR2/mDDR driver" + depends on ARCH_DAVINCI_DA8XX + help + This driver is for the DDR2/mDDR Memory Controller present on + Texas Instruments da8xx SoCs. It's used to tweak various memory + controller configuration options. + source "drivers/memory/samsung/Kconfig" source "drivers/memory/tegra/Kconfig" diff --git a/drivers/memory/Makefile b/drivers/memory/Makefile index b20ae38..e88097fb 100644 --- a/drivers/memory/Makefile +++ b/drivers/memory/Makefile @@ -17,6 +17,7 @@ obj-$(CONFIG_MVEBU_DEVBUS) += mvebu-devbus.o obj-$(CONFIG_TEGRA20_MC) += tegra20-mc.o obj-$(CONFIG_JZ4780_NEMC) += jz4780-nemc.o obj-$(CONFIG_MTK_SMI) += mtk-smi.o +obj-$(CONFIG_DA8XX_DDRCTL) += da8xx-ddrctl.o obj-$(CONFIG_SAMSUNG_MC) += samsung/ obj-$(CONFIG_TEGRA_MC) += tegra/ diff --git a/drivers/memory/da8xx-ddrctl.c b/drivers/memory/da8xx-ddrctl.c new file mode 100644 index 0000000..dcd0a61 --- /dev/null +++ b/drivers/memory/da8xx-ddrctl.c @@ -0,0 +1,77 @@ +/* + * TI da8xx DDR2/mDDR controller driver + * + * Copyright (C) 2016 BayLibre SAS + * + * Author: + * Bartosz Golaszewski + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ + +#include +#include +#include +#include + +#define DA8XX_DDR_CTL_BASE 0xB0000000 +#define DA8XX_PBBPR_OFFSET 0x00000020 +#define DA8XX_PBBPR_REG(p) ((p) + DA8XX_PBBPR_OFFSET) + +#define DA8XX_PBBPR_MAX 0xff + +static void da8xx_ddrctl_set_pbbpr(void __iomem *ddrctl, struct device *dev) +{ + struct device_node *node = dev->of_node; + u32 pr_old_count; + int ret; + + ret = of_property_read_u32(node, "ti,pr-old-count", &pr_old_count); + if (ret) + return; + + if (pr_old_count > DA8XX_PBBPR_MAX) { + dev_warn(dev, "priority raise old counter value too high\n"); + return; + } + + __raw_writel(pr_old_count, DA8XX_PBBPR_REG(ddrctl)); +} + +static int da8xx_ddrctl_probe(struct platform_device *pdev) +{ + struct device *dev = &pdev->dev; + void __iomem *ddrctl; + + ddrctl = ioremap(DA8XX_DDR_CTL_BASE, SZ_256); + if (!ddrctl) { + dev_err(dev, "unable to map memory controller registers\n"); + return -EIO; + } + + da8xx_ddrctl_set_pbbpr(ddrctl, dev); + + iounmap(ddrctl); + + return 0; +} + +static const struct of_device_id da8xx_ddrctl_of_match[] = { + { .compatible = "ti,da850-ddrctl", }, + { }, +}; + +static struct platform_driver da8xx_ddrctl_driver = { + .probe = da8xx_ddrctl_probe, + .driver = { + .name = "da8xx-ddrctl", + .of_match_table = da8xx_ddrctl_of_match, + }, +}; +module_platform_driver(da8xx_ddrctl_driver); + +MODULE_AUTHOR("Bartosz Golaszewski "); +MODULE_DESCRIPTION("TI da8xx DDR2/mDDR controller driver"); +MODULE_LICENSE("GPL v2");