From patchwork Tue Oct 25 06:48:00 2016 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Archit Taneja X-Patchwork-Id: 9394093 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 6C06460231 for ; Tue, 25 Oct 2016 06:48:18 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5E25129368 for ; Tue, 25 Oct 2016 06:48:18 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 52B31293B0; Tue, 25 Oct 2016 06:48:18 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BA68729316 for ; Tue, 25 Oct 2016 06:48:17 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 284AC6E668; Tue, 25 Oct 2016 06:48:17 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from smtp.codeaurora.org (smtp.codeaurora.org [198.145.29.96]) by gabe.freedesktop.org (Postfix) with ESMTPS id 935386E668 for ; Tue, 25 Oct 2016 06:48:15 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 7D32B61B3D; Tue, 25 Oct 2016 06:48:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1477378095; bh=yjAW3TystLJmB4RLUkI05bJq96tR6yvYCV2Ciem7Zvw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VWx1DLAJifHoK5ezct7q44RhrHP80XR6HZfjbVJJRcUSuwAroXQkb8bduztVinCXa fbWipfal77FXzEOGYYxcXLzSAPkDrC9gYSfY9CxS4bBmHd0VpJ/IGHmrHFIKbMf5FQ Xyao4tgSEBDNXHtropC1uFRRuO5v92KgSWX1dxos= Received: from localhost (unknown [202.46.23.61]) (using TLSv1.2 with cipher DHE-RSA-AES128-SHA (128/128 bits)) (No client certificate requested) (Authenticated sender: architt@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 2404161C0E; Tue, 25 Oct 2016 06:48:13 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1477378095; bh=yjAW3TystLJmB4RLUkI05bJq96tR6yvYCV2Ciem7Zvw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=VWx1DLAJifHoK5ezct7q44RhrHP80XR6HZfjbVJJRcUSuwAroXQkb8bduztVinCXa fbWipfal77FXzEOGYYxcXLzSAPkDrC9gYSfY9CxS4bBmHd0VpJ/IGHmrHFIKbMf5FQ Xyao4tgSEBDNXHtropC1uFRRuO5v92KgSWX1dxos= DMARC-Filter: OpenDMARC Filter v1.3.1 smtp.codeaurora.org 2404161C0E Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=pass smtp.mailfrom=architt@codeaurora.org From: Archit Taneja To: robdclark@gmail.com Subject: [PATCH 2/2] drm/msm: Don't provide 'is_enabled' PLL clk_ops Date: Tue, 25 Oct 2016 12:18:00 +0530 Message-Id: <1477378080-16087-3-git-send-email-architt@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1477378080-16087-1-git-send-email-architt@codeaurora.org> References: <1477378080-16087-1-git-send-email-architt@codeaurora.org> Cc: linux-arm-msm@vger.kernel.org, Stephen Boyd , dri-devel@lists.freedesktop.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP The DSI/HDMI PLLs in MSM require resources like interface clocks, power domains to be enabled before we can access their registers. The clock framework doesn't have a mechanism at the moment where we can tie such resources to a clock, so we make sure that the KMS driver enables these resources whenever a PLL is expected to be in use. One place where we can't ensure the resource dependencies are met is when the clock framework tries to disable unused clocks. The KMS driver doesn't know when the clock framework calls the is_enabled clk_op, and hence can't enable interface clocks/power domains beforehand. We remove the is_enabled clk_ops from the PLL clocks for now since they aren't mandatory. This needs to be revisited, since bootloaders can enable display, the enable count maintained by clock framework wouldn't work in such cases. Cc: Stephen Boyd Signed-off-by: Archit Taneja --- drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c | 10 ---------- drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c | 10 ---------- drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c | 13 ------------- 3 files changed, 33 deletions(-) diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c index 598fdaf..80b7fc3 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm.c @@ -248,15 +248,6 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, return 0; } -static int dsi_pll_28nm_clk_is_enabled(struct clk_hw *hw) -{ - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); - - return pll_28nm_poll_for_ready(pll_28nm, POLL_MAX_READS, - POLL_TIMEOUT_US); -} - static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -312,7 +303,6 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, .recalc_rate = dsi_pll_28nm_clk_recalc_rate, .prepare = msm_dsi_pll_helper_clk_prepare, .unprepare = msm_dsi_pll_helper_clk_unprepare, - .is_enabled = dsi_pll_28nm_clk_is_enabled, }; /* diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c index 38c90e1..b3d3ec7 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_28nm_8960.c @@ -156,15 +156,6 @@ static int dsi_pll_28nm_clk_set_rate(struct clk_hw *hw, unsigned long rate, return 0; } -static int dsi_pll_28nm_clk_is_enabled(struct clk_hw *hw) -{ - struct msm_dsi_pll *pll = hw_clk_to_pll(hw); - struct dsi_pll_28nm *pll_28nm = to_pll_28nm(pll); - - return pll_28nm_poll_for_ready(pll_28nm, POLL_MAX_READS, - POLL_TIMEOUT_US); -} - static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, unsigned long parent_rate) { @@ -206,7 +197,6 @@ static unsigned long dsi_pll_28nm_clk_recalc_rate(struct clk_hw *hw, .recalc_rate = dsi_pll_28nm_clk_recalc_rate, .prepare = msm_dsi_pll_helper_clk_prepare, .unprepare = msm_dsi_pll_helper_clk_unprepare, - .is_enabled = dsi_pll_28nm_clk_is_enabled, }; /* diff --git a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c index aa94a55..f3334e8 100644 --- a/drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c +++ b/drivers/gpu/drm/msm/hdmi/hdmi_phy_8996.c @@ -672,25 +672,12 @@ static void hdmi_8996_pll_unprepare(struct clk_hw *hw) { } -static int hdmi_8996_pll_is_enabled(struct clk_hw *hw) -{ - struct hdmi_pll_8996 *pll = hw_clk_to_pll(hw); - u32 status; - int pll_locked; - - status = hdmi_pll_read(pll, REG_HDMI_PHY_QSERDES_COM_C_READY_STATUS); - pll_locked = status & BIT(0); - - return pll_locked; -} - static struct clk_ops hdmi_8996_pll_ops = { .set_rate = hdmi_8996_pll_set_clk_rate, .round_rate = hdmi_8996_pll_round_rate, .recalc_rate = hdmi_8996_pll_recalc_rate, .prepare = hdmi_8996_pll_prepare, .unprepare = hdmi_8996_pll_unprepare, - .is_enabled = hdmi_8996_pll_is_enabled, }; static const char * const hdmi_pll_parents[] = {