From patchwork Fri Jan 20 07:38:31 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Andrzej Hajda X-Patchwork-Id: 9527657 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 4A67760434 for ; Fri, 20 Jan 2017 07:40:09 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 3A8BD28452 for ; Fri, 20 Jan 2017 07:40:09 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 2EB6E28620; Fri, 20 Jan 2017 07:40:09 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id AE69128452 for ; Fri, 20 Jan 2017 07:40:08 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 7A50C6EB4F; Fri, 20 Jan 2017 07:39:17 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mailout2.w1.samsung.com (mailout2.w1.samsung.com [210.118.77.12]) by gabe.freedesktop.org (Postfix) with ESMTPS id 64A296EB22 for ; Fri, 20 Jan 2017 07:38:59 +0000 (UTC) Received: from eucas1p1.samsung.com (unknown [182.198.249.206]) by mailout2.w1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTP id <0OK200F6YIKXNX50@mailout2.w1.samsung.com> for dri-devel@lists.freedesktop.org; Fri, 20 Jan 2017 07:38:57 +0000 (GMT) Received: from eusmges5.samsung.com (unknown [203.254.199.245]) by eucas1p1.samsung.com (KnoxPortal) with ESMTP id 20170120073856eucas1p186ec8d13811ecfce23eab80e3636d4b9~bas5ebMNn0245502455eucas1p1k; Fri, 20 Jan 2017 07:38:56 +0000 (GMT) Received: from eucas1p1.samsung.com ( [182.198.249.206]) by eusmges5.samsung.com (EUCPMTA) with SMTP id A3.A1.17477.09EB1885; Fri, 20 Jan 2017 07:38:56 +0000 (GMT) Received: from eusmgms1.samsung.com (unknown [182.198.249.179]) by eucas1p1.samsung.com (KnoxPortal) with ESMTP id 20170120073856eucas1p1fa2a6007c5073f08c62f2c98aadb1726~bas452Z-o0440904409eucas1p1Y; Fri, 20 Jan 2017 07:38:56 +0000 (GMT) X-AuditID: cbfec7f5-f79d06d000004445-fc-5881be900eab Received: from eusync1.samsung.com ( [203.254.199.211]) by eusmgms1.samsung.com (EUCPMTA) with SMTP id 85.08.06687.BCEB1885; Fri, 20 Jan 2017 07:39:55 +0000 (GMT) Received: from AMDC2768.DIGITAL.local ([106.120.43.17]) by eusync1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OK200LE1IKT7D70@eusync1.samsung.com>; Fri, 20 Jan 2017 07:38:56 +0000 (GMT) From: Andrzej Hajda To: Archit Taneja , dri-devel@lists.freedesktop.org Subject: [PATCH 05/24] drm/bridge/sii8620: initial support for eCBUS-S mode Date: Fri, 20 Jan 2017 08:38:31 +0100 Message-id: <1484897930-1275-6-git-send-email-a.hajda@samsung.com> X-Mailer: git-send-email 2.7.4 In-reply-to: <1484897930-1275-1-git-send-email-a.hajda@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrLIsWRmVeSWpSXmKPExsWy7djPc7oT9jVGGHTdl7W4te4cq0VTx1tW i40z1rNaXPn6ns1i0v0JLBZrj9xld2DzuNzXy+Rxv/s4k0ffllWMAcxRXDYpqTmZZalF+nYJ XBkbP11nL+jQrdgxYxljA2OHahcjJ4eEgInEzQfzGSFsMYkL99azdTFycQgJLGWUOLmygxHC +cwoMfvIVjaYjgdvF7FDJJYxSjz7uJQFwvnPKLFl0T9WkCo2AU2Jv5tvgnWICHhLzFndB7aD WWA9o8S1U3EgtjBQfM3SpUwgNouAqsS//1fA6nkFnCTmrLzFArFNTuLmuU5mEJtTwFni/I0v TCDLJATus0lsv30NqIEDyJGV2HSAGaLeReLbz61Q/whLvDq+hR3ClpHo7DgI1dvNKPGp/wQ7 hDOFUeLfhxlQ3dYSh49fZIW4lE9i0rbpzBALeCU62oQgSjwkbrzaCbXAUeLf30nQoJjGKLFx /nq2CYwyCxgZVjGKpJYW56anFpvqFSfmFpfmpesl5+duYgRG6ul/x7/uYFx6zOoQowAHoxIP 744TDRFCrIllxZW5hxglOJiVRHh71jdGCPGmJFZWpRblxxeV5qQWH2KU5mBREufds+BKuJBA emJJanZqakFqEUyWiYNTqoEx6YnAjXPdXCz+cfoTv+vxS80ovLIkUbrmWNTuO0o/561krRQN ZX23d0Li/A2PQnvXJNp8Z3Pi0+V6cWzRwaOX4v27JNwjTLJP7v98Z8epV24Ll0fHrH5+NXDO e9me5euNW6esDE9Iei4aGONw3edOIb++wfkOxSvnehw+5De7bOvd6nv01a6zSizFGYmGWsxF xYkAhDX6Y9ACAAA= X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrNLMWRmVeSWpSXmKPExsVy+t/xy7qn9zVGGGx5ymVxa905Voumjres FhtnrGe1uPL1PZvFpPsTWCzWHrnL7sDmcbmvl8njfvdxJo++LasYA5ij3GwyUhNTUosUUvOS 81My89JtlUJD3HQtlBTyEnNTbZUidH1DgpQUyhJzSoE8IwM04OAc4B6spG+X4Jax8dN19oIO 3YodM5YxNjB2qHYxcnJICJhIPHi7iB3CFpO4cG89WxcjF4eQwBJGibXLLrFCOI1MEvfnr2cC qWIT0JT4u/kmG4gtIuAtMWd1HyNIEbPAekaJqY//go0SBkqsWboUrIFFQFXi3/8rYA28Ak4S c1beYoFYJydx81wnM4jNKeAscf7GF6B6DqBtThLXZslOYORdwMiwilEktbQ4Nz232FCvODG3 uDQvXS85P3cTIzBgtx37uXkH46WNwYcYBTgYlXh4E441RAixJpYVV+YeYpTgYFYS4e1Z3xgh xJuSWFmVWpQfX1Sak1p8iNEU6KaJzFKiyfnAaMoriTc0MTS3NDQytrAwNzJSEuct+XAlXEgg PbEkNTs1tSC1CKaPiYNTqoGRgze2YfWJyKIfS9ffX9dSXXNtudSrs6evKz/2fOBl/7refoLw DT+tX/ziwZe+ZnBssWFlnFR4ca2K0dyTmhaN1vox2tJb7i8QNZurv5o7gSO4IKlD8Fghk/LR i8pVClNMD7tfe1adb6y/rzbpyB/57/u38gav/PCa6U3HoZTn1Wd+iR9ZG8ivxFKckWioxVxU nAgARM4sfG4CAAA= X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170120073856eucas1p1fa2a6007c5073f08c62f2c98aadb1726 X-Msg-Generator: CA X-Sender-IP: 182.198.249.179 X-Local-Sender: =?UTF-8?B?QW5kcnplaiBIYWpkYRtTUlBPTC1LZXJuZWwgKFRQKRvsgrw=?= =?UTF-8?B?7ISx7KCE7J6QG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Global-Sender: =?UTF-8?B?QW5kcnplaiBIYWpkYRtTUlBPTC1LZXJuZWwgKFRQKRtTYW1z?= =?UTF-8?B?dW5nIEVsZWN0cm9uaWNzG1NlbmlvciBTb2Z0d2FyZSBFbmdpbmVlcg==?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 201P X-HopCount: 7 X-CMS-RootMailID: 20170120073856eucas1p1fa2a6007c5073f08c62f2c98aadb1726 X-RootMTR: 20170120073856eucas1p1fa2a6007c5073f08c62f2c98aadb1726 References: <1484897930-1275-1-git-send-email-a.hajda@samsung.com> Cc: Marek Szyprowski , Bartlomiej Zolnierkiewicz X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP The Single-ended eCBUS Mode (eCBUS-S) mode provides 60 Mb/s full-duplex bidirectional traffic for three channels: - CBUS data (CBUS1 channel), - High-bandwidth MHL data (eMSC channel), - tunneling data (T-CBUS channel). It is required to fully support MHL3 dongles. Signed-off-by: Andrzej Hajda --- drivers/gpu/drm/bridge/sil-sii8620.c | 104 ++++++++++++++++++++++++++++++++++- drivers/gpu/drm/bridge/sil-sii8620.h | 5 ++ 2 files changed, 107 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/bridge/sil-sii8620.c b/drivers/gpu/drm/bridge/sil-sii8620.c index cde0074..9f9fd99 100644 --- a/drivers/gpu/drm/bridge/sil-sii8620.c +++ b/drivers/gpu/drm/bridge/sil-sii8620.c @@ -104,6 +104,7 @@ static void sii8620_fetch_edid(struct sii8620 *ctx); static void sii8620_set_upstream_edid(struct sii8620 *ctx); static void sii8620_enable_hpd(struct sii8620 *ctx); static void sii8620_mhl_disconnected(struct sii8620 *ctx); +static void sii8620_disconnect(struct sii8620 *ctx); static int sii8620_clear_error(struct sii8620 *ctx) { @@ -1016,13 +1017,44 @@ static void sii8620_mhl_init(struct sii8620 *ctx) sii8620_mt_set_int(ctx, MHL_INT_REG(RCHANGE), MHL_INT_RC_DCAP_CHG); } +static void sii8620_emsc_enable(struct sii8620 *ctx) +{ + u8 reg; + + sii8620_setbits(ctx, REG_GENCTL, BIT_GENCTL_EMSC_EN + | BIT_GENCTL_CLR_EMSC_RFIFO + | BIT_GENCTL_CLR_EMSC_XFIFO, ~0); + sii8620_setbits(ctx, REG_GENCTL, BIT_GENCTL_CLR_EMSC_RFIFO + | BIT_GENCTL_CLR_EMSC_XFIFO, 0); + sii8620_setbits(ctx, REG_COMMECNT, BIT_COMMECNT_I2C_TO_EMSC_EN, ~0); + reg = sii8620_readb(ctx, REG_EMSCINTR); + sii8620_write(ctx, REG_EMSCINTR, reg); + sii8620_write(ctx, REG_EMSCINTRMASK, BIT_EMSCINTR_SPI_DVLD); +} + +static int sii8620_wait_for_fsm_state(struct sii8620 *ctx, u8 state) +{ + int i; + + for (i = 0; i < 10; ++i) { + u8 s = sii8620_readb(ctx, REG_COC_STAT_0); + + if ((s & MSK_COC_STAT_0_FSM_STATE) == state) + return 0; + if (s & BIT_COC_STAT_0_PLL_LOCKED) + return -EBUSY; + usleep_range(4000, 6000); + } + return -ETIMEDOUT; +} + static void sii8620_set_mode(struct sii8620 *ctx, enum sii8620_mode mode) { + int ret; + if (ctx->mode == mode) return; - ctx->mode = mode; - switch (mode) { case CM_MHL1: sii8620_write_seq_static(ctx, @@ -1032,11 +1064,46 @@ static void sii8620_set_mode(struct sii8620 *ctx, enum sii8620_mode mode) | BIT_DPD_OSC_EN, REG_COC_INTR_MASK, 0 ); + ctx->mode = mode; break; case CM_MHL3: sii8620_write(ctx, REG_M3_CTRL, VAL_M3_CTRL_MHL3_VALUE); + ctx->mode = mode; + return; + case CM_ECBUS_S: + sii8620_emsc_enable(ctx); + sii8620_write_seq_static(ctx, + REG_TTXSPINUMS, 4, + REG_TRXSPINUMS, 4, + REG_TTXHSICNUMS, 0x14, + REG_TRXHSICNUMS, 0x14, + REG_TTXTOTNUMS, 0x18, + REG_TRXTOTNUMS, 0x18, + REG_PWD_SRST, BIT_PWD_SRST_COC_DOC_RST + | BIT_PWD_SRST_CBUS_RST_SW_EN, + REG_MHL_COC_CTL1, 0xbd, + REG_PWD_SRST, BIT_PWD_SRST_CBUS_RST_SW_EN, + REG_COC_CTLB, 0x01, + REG_COC_CTL0, 0x5c, + REG_COC_CTL14, 0x03, + REG_COC_CTL15, 0x80, + REG_MHL_DP_CTL6, BIT_MHL_DP_CTL6_DP_TAP1_SGN + | BIT_MHL_DP_CTL6_DP_TAP1_EN + | BIT_MHL_DP_CTL6_DT_PREDRV_FEEDCAP_EN, + REG_MHL_DP_CTL8, 0x03 + ); + ret = sii8620_wait_for_fsm_state(ctx, 0x03); + sii8620_write_seq_static(ctx, + REG_COC_CTL14, 0x00, + REG_COC_CTL15, 0x80 + ); + if (!ret) + sii8620_write(ctx, REG_CBUS3_CNVT, 0x85); + else + sii8620_disconnect(ctx); return; case CM_DISCONNECTED: + ctx->mode = mode; break; default: dev_err(ctx->dev, "%s mode %d not supported\n", __func__, mode); @@ -1229,12 +1296,45 @@ static void sii8620_msc_mr_write_stat(struct sii8620 *ctx) sii8620_status_changed_path(ctx); } +static void sii8620_ecbus_up(struct sii8620 *ctx, int ret) +{ + if (ret < 0) + return; + + sii8620_set_mode(ctx, CM_ECBUS_S); +} + +static void sii8620_got_ecbus_speed(struct sii8620 *ctx, int ret) +{ + if (ret < 0) + return; + + sii8620_mt_write_stat(ctx, MHL_XDS_REG(CURR_ECBUS_MODE), + MHL_XDS_ECBUS_S | MHL_XDS_SLOT_MODE_8BIT); + sii8620_mt_rap(ctx, MHL_RAP_CBUS_MODE_UP); + sii8620_mt_set_cont(ctx, sii8620_ecbus_up); +} + static void sii8620_msc_mr_set_int(struct sii8620 *ctx) { u8 ints[MHL_INT_SIZE]; sii8620_read_buf(ctx, REG_MHL_INT_0, ints, MHL_INT_SIZE); sii8620_write_buf(ctx, REG_MHL_INT_0, ints, MHL_INT_SIZE); + + if (ints[MHL_INT_RCHANGE] & MHL_INT_RC_DCAP_CHG) { + switch (ctx->mode) { + case CM_MHL3: + sii8620_mt_read_xdevcap_reg(ctx, MHL_XDC_ECBUS_SPEEDS); + sii8620_mt_set_cont(ctx, sii8620_got_ecbus_speed); + break; + case CM_ECBUS_S: + sii8620_mt_read_devcap(ctx, true); + break; + default: + break; + } + } } static struct sii8620_mt_msg *sii8620_msc_msg_first(struct sii8620 *ctx) diff --git a/drivers/gpu/drm/bridge/sil-sii8620.h b/drivers/gpu/drm/bridge/sil-sii8620.h index 6ff616a..3ee4e7e 100644 --- a/drivers/gpu/drm/bridge/sil-sii8620.h +++ b/drivers/gpu/drm/bridge/sil-sii8620.h @@ -841,6 +841,8 @@ #define MSK_MHL_DP_CTL7_DT_DRV_VBIAS_CASCTL 0xf0 #define MSK_MHL_DP_CTL7_DT_DRV_IREF_CTL 0x0f +#define REG_MHL_DP_CTL8 0x0352 + /* Tx Zone Ctl1, default value: 0x00 */ #define REG_TX_ZONE_CTL1 0x0361 #define VAL_TX_ZONE_CTL1_TX_ZONE_CTRL_MODE 0x08 @@ -1088,6 +1090,9 @@ /* CoC Status, default value: 0x00 */ #define REG_COC_STAT_0 0x0700 +#define BIT_COC_STAT_0_PLL_LOCKED BIT(7) +#define MSK_COC_STAT_0_FSM_STATE 0x0f + #define REG_COC_STAT_1 0x0701 #define REG_COC_STAT_2 0x0702 #define REG_COC_STAT_3 0x0703