From patchwork Tue Mar 7 17:14:15 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 9609509 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1EB4F602B4 for ; Tue, 7 Mar 2017 17:14:33 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id F0E9128491 for ; Tue, 7 Mar 2017 17:14:32 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id E35C028507; Tue, 7 Mar 2017 17:14:32 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id DEE7428491 for ; Tue, 7 Mar 2017 17:14:31 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2E3D56E099; Tue, 7 Mar 2017 17:14:29 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from smtp.codeaurora.org (smtp.codeaurora.org [198.145.29.96]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2EC706E099; Tue, 7 Mar 2017 17:14:28 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 19E95607A5; Tue, 7 Mar 2017 17:14:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1488906868; bh=Dhp5WVHPwLduY+l7ipSKptg/oD5FjedVB7SqZt5VLP0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=fZYJfoGuNbpDcIp3HQd/dZZQjPZUmpYVfEzTE6baHJzoE+G3v7CZXjHfR3vjnMhDj lfRpsRowYLObDy/JapBSBNKQJWddEfmiNpISHQW+eplQ2KK0sHKuSXvVg2yzIWpTsc e8qSUs9xe3zq+dqwhCQSAK2yDHn4ZqQGfGADh6OE= Received: from jcrouse-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 613CC60780; Tue, 7 Mar 2017 17:14:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1488906867; bh=Dhp5WVHPwLduY+l7ipSKptg/oD5FjedVB7SqZt5VLP0=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=LvNcZlDeU5iKLr/u2acHtK6Jtcod0FyOc1YVDAWqCaajs/i5snxKcbktMpNGFHPMC NZTT2AkCbX1qQsUsIcpdtP2BnVXfLIhGJ2L9HSq0nf/FKDpWTp20AOY+HbfHfwFH99 b/7kmvcOTX+cT723iuHMiLuKAmGabSMXyBACDKKo= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 613CC60780 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: freedreno@lists.freedesktop.org Subject: [PATCH 1/6] drm/msm: Enable 64 bit mode by default Date: Tue, 7 Mar 2017 10:14:15 -0700 Message-Id: <1488906860-11073-2-git-send-email-jcrouse@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1488906860-11073-1-git-send-email-jcrouse@codeaurora.org> References: <1488906860-11073-1-git-send-email-jcrouse@codeaurora.org> Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP A5XX GPUs can be run in either 32 or 64 bit mode. The GPU registers and the microcode use 64 bit virtual addressing in either case but the upper 32 bits are ignored if the GPU is in 32 bit mode. There is no performance disadvantage to remaining in 64 bit mode even if we are only generating 32 bit addresses so switch over now to prepare for using addresses above 4G for targets that support them. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 14 ++++++++++++++ drivers/gpu/drm/msm/msm_iommu.c | 7 +++---- 2 files changed, 17 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index fef1541..06238b7 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -800,6 +800,20 @@ static int a5xx_hw_init(struct msm_gpu *gpu) REG_A5XX_RBBM_SECVID_TSB_TRUSTED_BASE_HI, 0x00000000); gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_TRUSTED_SIZE, 0x00000000); + /* Put the GPU into 64 bit by default */ + gpu_write(gpu, REG_A5XX_CP_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_VSC_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_GRAS_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_RB_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_PC_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_HLSQ_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_VFD_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_VPC_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_UCHE_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_SP_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_TPL1_ADDR_MODE_CNTL, 0x1); + gpu_write(gpu, REG_A5XX_RBBM_SECVID_TSB_ADDR_MODE_CNTL, 0x1); + /* Load the GPMU firmware before starting the HW init */ a5xx_gpmu_ucode_init(gpu); diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c index 7521582..d520db2 100644 --- a/drivers/gpu/drm/msm/msm_iommu.c +++ b/drivers/gpu/drm/msm/msm_iommu.c @@ -34,10 +34,9 @@ static int msm_fault_handler(struct iommu_domain *domain, struct device *dev, if (iommu->base.handler) ret = iommu->base.handler(iommu->base.arg, iova, flags); else - pr_warn_ratelimited("*** fault: iova=%08lx, flags=%d\n", iova, flags); + pr_warn_ratelimited("*** fault: iova=%16lx, flags=%d\n", iova, flags); iommu_domain_resume(domain, false); - return 0; } @@ -104,7 +103,7 @@ static int msm_iommu_map(struct msm_mmu *mmu, uint64_t iova, dma_addr_t pa = sg_phys(sg) - sg->offset; size_t bytes = sg->length + sg->offset; - VERB("map[%d]: %08lx %08lx(%zx)", i, da, (unsigned long)pa, bytes); + VERB("map[%d]: %16lx %16lx(%zx)", i, da, (unsigned long)pa, bytes); ret = iommu_map(domain, da, pa, bytes, prot); if (ret) @@ -143,7 +142,7 @@ static int msm_iommu_unmap(struct msm_mmu *mmu, uint64_t iova, if (unmapped < bytes) return unmapped; - VERB("unmap[%d]: %08lx(%zx)", i, da, bytes); + VERB("unmap[%d]: %16lx(%zx)", i, da, bytes); BUG_ON(!PAGE_ALIGNED(bytes));