From patchwork Tue Mar 7 17:14:18 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 9609513 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 3E590602B4 for ; Tue, 7 Mar 2017 17:14:38 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 1F72928491 for ; Tue, 7 Mar 2017 17:14:38 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 144F128507; Tue, 7 Mar 2017 17:14:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id B02C028491 for ; Tue, 7 Mar 2017 17:14:37 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A706D6E780; Tue, 7 Mar 2017 17:14:30 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from smtp.codeaurora.org (smtp.codeaurora.org [198.145.29.96]) by gabe.freedesktop.org (Postfix) with ESMTPS id BFB216E776; Tue, 7 Mar 2017 17:14:29 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1000) id A44A66079A; Tue, 7 Mar 2017 17:14:29 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1488906869; bh=cdgY6ke8wIt/DJD6gKzJ/SpREv1LfbXuXc/E02N8vJw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PEqbxRW21svxG4RsXMHsB5+9xwG0kC3pktIv3ni+yn/R7XMzlT2ChghnLS3zwKaCL 2A6lFnDvn+TOBTwMQzmjLUwgADKSEwF1bS3Ztrv9tSBdcalL/7466CG+fkLVm8ZXXq nt9rGAVODRiLa2ylgvyl1398aNiItruV6iGWUlFs= Received: from jcrouse-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id E76746079A; Tue, 7 Mar 2017 17:14:28 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1488906869; bh=cdgY6ke8wIt/DJD6gKzJ/SpREv1LfbXuXc/E02N8vJw=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=PEqbxRW21svxG4RsXMHsB5+9xwG0kC3pktIv3ni+yn/R7XMzlT2ChghnLS3zwKaCL 2A6lFnDvn+TOBTwMQzmjLUwgADKSEwF1bS3Ztrv9tSBdcalL/7466CG+fkLVm8ZXXq nt9rGAVODRiLa2ylgvyl1398aNiItruV6iGWUlFs= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org E76746079A Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: freedreno@lists.freedesktop.org Subject: [PATCH 4/6] drm/msm: Use TTBR1 for kernel side GPU buffer objects Date: Tue, 7 Mar 2017 10:14:18 -0700 Message-Id: <1488906860-11073-5-git-send-email-jcrouse@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1488906860-11073-1-git-send-email-jcrouse@codeaurora.org> References: <1488906860-11073-1-git-send-email-jcrouse@codeaurora.org> Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Use a TTBR1 pagetable for the GPU IOMMU domain and map all the GPU kernel side buffer objects into that range. This will make it easier to switch out TTBR0 for per-process pagetables. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 18 ++++++++++++++++-- drivers/gpu/drm/msm/msm_iommu.c | 7 +++++++ 2 files changed, 23 insertions(+), 2 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index b41bd88..d7864ac 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -418,8 +418,22 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, adreno_gpu_config.ioname = "kgsl_3d0_reg_memory"; adreno_gpu_config.irqname = "kgsl_3d0_irq"; - adreno_gpu_config.va_start = SZ_16M; - adreno_gpu_config.va_end = 0xffffffff; + if (adreno_gpu->revn >= 500) { + /* + * By default map all A5XX buffers into the TTBR1 va space. + * If per-instance pagetables are used then they will + * use their own address space and the default domain will only + * be used for kernel buffers. If per-instance pagetables aren't + * enabled then we'll end up using the TTBR1 range as the + * default global pagetable but that's okay because we have + * plenty of room. + */ + adreno_gpu_config.va_start = 0xfffffff800000000ULL; + adreno_gpu_config.va_end = 0xfffffff8ffffffffULL; + } else { + adreno_gpu_config.va_start = SZ_16M; + adreno_gpu_config.va_end = 0xffffffff; + } adreno_gpu_config.nr_rings = nr_rings; diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c index c1bfc92..cc82410 100644 --- a/drivers/gpu/drm/msm/msm_iommu.c +++ b/drivers/gpu/drm/msm/msm_iommu.c @@ -83,6 +83,13 @@ static int msm_iommu_v2_attach(struct msm_mmu *mmu, const char * const *names, int cnt) { struct msm_iommu *iommu = to_msm_iommu(mmu); + int val = 1; + + /* Use TTBR1 if it exists */ + /* FIXME: This should only be for GPU and in theory only for A5XX */ + + iommu_domain_set_attr(iommu->domain, DOMAIN_ATTR_ENABLE_TTBR1, + &val); return iommu_attach_device(iommu->domain, mmu->dev); }