From patchwork Fri Apr 21 17:19:47 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Sylwester Nawrocki/Kernel \\(PLT\\) /SRPOL/Staff Engineer/Samsung Electronics" X-Patchwork-Id: 9693207 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 8AC07601D4 for ; Fri, 21 Apr 2017 17:20:38 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 7756928607 for ; Fri, 21 Apr 2017 17:20:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 6C29A2863D; Fri, 21 Apr 2017 17:20:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id EF3B828607 for ; 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Sat, 22 Apr 2017 02:20:30 +0900 (KST) Received: from epcpsbgm2new.samsung.com (u27.gpu120.samsung.co.kr [203.254.230.27]) by epcas5p1.samsung.com (KnoxPortal) with ESMTP id 20170421172029epcas5p1b32ed135c5e0f1b86fbcc54279126349~3eVoD3a8H2347523475epcas5p12; Fri, 21 Apr 2017 17:20:29 +0000 (GMT) X-AuditID: b6c32a58-f79586d000001c40-6d-58fa3f5dfc16 Received: from epmmp1.local.host ( [203.254.227.16]) by epcpsbgm2new.samsung.com (EPCPMTA) with SMTP id E4.F8.05013.C5F3AF85; Sat, 22 Apr 2017 02:20:28 +0900 (KST) Received: from AMDC3061.digital.local ([106.116.147.40]) by mmp1.samsung.com (Oracle Communications Messaging Server 7.0.5.31.0 64bit (built May 5 2014)) with ESMTPA id <0OOR00KJBS560G40@mmp1.samsung.com>; Sat, 22 Apr 2017 02:20:28 +0900 (KST) From: Sylwester Nawrocki To: linux-samsung-soc@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, alsa-devel@alsa-project.org, devicetree@vger.kernel.org Subject: [PATCH RFC 3/7] clk: samsung: exynos542x: Add EPLL rate table Date: Fri, 21 Apr 2017 19:19:47 +0200 Message-id: <1492795191-31298-4-git-send-email-s.nawrocki@samsung.com> X-Mailer: git-send-email 1.9.1 In-reply-to: <1492795191-31298-1-git-send-email-s.nawrocki@samsung.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFvrBIsWRmVeSWpSXmKPExsWy7bCmlm6c/a8Ig83eFlcuHmKy2DhjPavF 1IdP2Cyuf3nOajH/yDlWiytf37NZTLo/gcXizds1TBYv7l1ksTh/fgO7xceee6wWM87vY7Jo 3XuE3eLwm3Ygd/JLNgd+jw2fm9g8Nq3qZPO4332cyWNL/112j74tqxg9Pm+SC2CL4rJJSc3J LEst0rdL4MpYf72HsWC7cMWCl/OZGxiPC3QxcnJICJhIHFx1mxXCFpO4cG89WxcjF4eQwFJG iRMP/zOCJIQE2pkkVvVLwzRc65nGAlG0nFFi8tWTrBDOL0aJ6R33mUCq2AQMJXqP9jGCJEQE 5jFKXNs2AWwus8A/RolpFyazg1QJC7hJHN87gxnEZhFQlVh+pBNoFAcHL1D8wrxciHVyEieP TQYLcwq4S1x8yg4yRkJgE7vEol8dLCBxCQFZiU0HmCHKXSTmTGxggbCFJV4d38IOYUtL/F16 ixGitx/otTXNUM4MRok77ROYIKqsJQ4fvwgODGYBPone30+YIBbwSnS0CUGUeEi8+HEZqtxR 4vnXHmaI72cxStxc/IllAqPMAkaGVYxiqQXFuempxaYFJnrFibnFpXnpesn5uZsYwelBK2IH 478ZQYcYBTgYlXh4Gdh/RQixJpYVV+YeYpTgYFYS4fXWBwrxpiRWVqUW5ccXleakFh9ilOZg URLnVV95LUJIID2xJDU7NbUgtQgmy8TBKdXAuLtoxSIF/fBuVseCe8ui2202rKiwti8y8q4P P1Xqnz5f5NBBjmOfGa9oRTdtNNgdlLREKKXB/fjVb69ef3n2/Ypa7cYjW+ar7uvjlJEum5ZX tH7NB+4j25cdWbsq+NlZruxb57W3XV7q+PkbY0eW8RkWp3mbXvR/KWtW8bB+ZMK91OrtQSuf zUosxRmJhlrMRcWJAEf7+zMLAwAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFprFIsWRmVeSWpSXmKPExsVy+t9jAd0Y+18RBm8uWVhcuXiIyWLjjPWs FlMfPmGzuP7lOavF/CPnWC2ufH3PZjHp/gQWizdv1zBZvLh3kcXi/PkN7BYfe+6xWsw4v4/J onXvEXaLw2/agdzJL9kc+D02fG5i89i0qpPN4373cSaPLf132T36tqxi9Pi8SS6ALcrNJiM1 MSW1SCE1Lzk/JTMv3VYpNMRN10JJIS8xN9VWKULXNyRISaEsMacUyDMyQAMOzgHuwUr6dglu Geuv9zAWbBeuWPByPnMD43GBLkZODgkBE4lrPdNYIGwxiQv31rN1MXJxCAksZZTY+LidCcL5 BeQsn8EOUsUmYCjRe7SPESQhIjCPUWLDybVgDrPAP0aJY039YLOEBdwkju+dwQxiswioSiw/ 0snaxcjBwQsUvzAvF2KdnMTJY5PBwpwC7hIXn4LNFwKqWNp/mXUCI+8CRoZVjBKpBckFxUnp uUZ5qeV6xYm5xaV56XrJ+bmbGMHx8kx6B+PhXe6HGAU4GJV4eFew/IoQYk0sK67MPcQowcGs JMLrrQ8U4k1JrKxKLcqPLyrNSS0+xGgKdNZEZinR5HxgLOeVxBuamJuYGxtYmFtamhgpifM2 zn4WLiSQnliSmp2aWpBaBNPHxMEp1cCoO/3puu9lOVs//p/nJVEg3JvMtN1XsdxQreveQ0eX Is/m8gSGaE3u8Dl+3Uuu/v537MXx5ZM80q/O5eeru/5tdYh780OLJja3w9FWtZP0+Myv2Tyy zF7EwGEa8auO60vll2dru4ImzQ+ePOWhoKG+j2KUsN+ST56TD81vFpVZc+j1hjS26ROVWIoz Eg21mIuKEwHU8UQFrQIAAA== X-MTR: 20000000000000000@CPGS X-CMS-MailID: 20170421172029epcas5p1b32ed135c5e0f1b86fbcc54279126349 X-Msg-Generator: CA X-Sender-IP: 203.254.230.27 X-Local-Sender: =?UTF-8?B?U3lsd2VzdGVyIE5hd3JvY2tpG1NSUE9MLUtlcm5lbCAoVFAp?= =?UTF-8?B?G+yCvOyEseyghOyekBtTZW5pb3IgU29mdHdhcmUgRW5naW5lZXI=?= X-Global-Sender: =?UTF-8?B?U3lsd2VzdGVyIE5hd3JvY2tpG1NSUE9MLUtlcm5lbCAoVFAp?= =?UTF-8?B?G1NhbXN1bmcgRWxlY3Ryb25pY3MbU2VuaW9yIFNvZnR3YXJlIEVuZ2luZWVy?= X-Sender-Code: =?UTF-8?B?QzEwG0VIURtDMTBDRDAyQ0QwMjczOTI=?= CMS-TYPE: 105P X-HopCount: 7 X-CMS-RootMailID: 20170421172029epcas5p1b32ed135c5e0f1b86fbcc54279126349 X-RootMTR: 20170421172029epcas5p1b32ed135c5e0f1b86fbcc54279126349 References: <1492795191-31298-1-git-send-email-s.nawrocki@samsung.com> Cc: javier@osg.samsung.com, b.zolnierkie@samsung.com, sw0312.kim@samsung.com, krzk@kernel.org, cw00.choi@samsung.com, broonie@kernel.org, Sylwester Nawrocki , robh+dt@kernel.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP A specific clock rate table is added for EPLL so it is possible to set frequency of the EPLL output clock as multiple of various audio sampling rates. Signed-off-by: Sylwester Nawrocki Reviewed-by: Krzysztof Kozlowski --- drivers/clk/samsung/clk-exynos5420.c | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-) diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c index 87c711a..6fbd6ae 100644 --- a/drivers/clk/samsung/clk-exynos5420.c +++ b/drivers/clk/samsung/clk-exynos5420.c @@ -1279,6 +1279,22 @@ static void __init exynos5420_clk_sleep_init(void) {} PLL_35XX_RATE(200000000, 200, 3, 3), }; +static const struct samsung_pll_rate_table exynos5420_epll_24mhz_tbl[] = { + PLL_36XX_RATE(600000000U, 100, 2, 1, 0), + PLL_36XX_RATE(400000000U, 200, 2, 2, 0), + PLL_36XX_RATE(393216000U, 197, 3, 2, 25690), + PLL_36XX_RATE(361267200U, 301, 5, 2, 3671), + PLL_36XX_RATE(200000000U, 200, 3, 3, 0), + PLL_36XX_RATE(196608000U, 197, 3, 3, -25690), + PLL_36XX_RATE(180633600U, 301, 5, 3, 3671), + PLL_36XX_RATE(131072000U, 131, 3, 3, 4719), + PLL_36XX_RATE(100000000U, 200, 3, 4, 0), + PLL_36XX_RATE( 65536000U, 131, 3, 4, 4719), + PLL_36XX_RATE( 49152000U, 197, 3, 5, 25690), + PLL_36XX_RATE( 45158400U, 301, 5, 3, 3671), + PLL_36XX_RATE( 32768000U, 131, 3, 5, 4719), +}; + static struct samsung_pll_clock exynos5x_plls[nr_plls] __initdata = { [apll] = PLL(pll_2550, CLK_FOUT_APLL, "fout_apll", "fin_pll", APLL_LOCK, APLL_CON0, NULL), @@ -1286,7 +1302,7 @@ static void __init exynos5420_clk_sleep_init(void) {} CPLL_CON0, NULL), [dpll] = PLL(pll_2550, CLK_FOUT_DPLL, "fout_dpll", "fin_pll", DPLL_LOCK, DPLL_CON0, NULL), - [epll] = PLL(pll_2650, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK, + [epll] = PLL(pll_36xx, CLK_FOUT_EPLL, "fout_epll", "fin_pll", EPLL_LOCK, EPLL_CON0, NULL), [rpll] = PLL(pll_2650, CLK_FOUT_RPLL, "fout_rpll", "fin_pll", RPLL_LOCK, RPLL_CON0, NULL), @@ -1401,7 +1417,7 @@ static void __init exynos5x_clk_init(struct device_node *np, if (_get_rate("fin_pll") == 24 * MHZ) { exynos5x_plls[apll].rate_table = exynos5420_pll2550x_24mhz_tbl; - exynos5x_plls[epll].rate_table = exynos5420_pll2550x_24mhz_tbl; + exynos5x_plls[epll].rate_table = exynos5420_epll_24mhz_tbl; exynos5x_plls[kpll].rate_table = exynos5420_pll2550x_24mhz_tbl; exynos5x_plls[bpll].rate_table = exynos5420_pll2550x_24mhz_tbl; }