@@ -40,6 +40,7 @@
extern bool hang_debug;
static void a3xx_dump(struct msm_gpu *gpu);
+static bool a3xx_idle(struct msm_gpu *gpu);
static bool a3xx_me_init(struct msm_gpu *gpu)
{
@@ -65,7 +66,7 @@ static bool a3xx_me_init(struct msm_gpu *gpu)
OUT_RING(ring, 0x00000000);
gpu->funcs->flush(gpu);
- return gpu->funcs->idle(gpu);
+ return a3xx_idle(gpu);
}
static int a3xx_hw_init(struct msm_gpu *gpu)
@@ -446,7 +447,6 @@ static void a3xx_dump(struct msm_gpu *gpu)
.last_fence = adreno_last_fence,
.submit = adreno_submit,
.flush = adreno_flush,
- .idle = a3xx_idle,
.irq = a3xx_irq,
.destroy = a3xx_destroy,
#ifdef CONFIG_DEBUG_FS
@@ -31,6 +31,7 @@
extern bool hang_debug;
static void a4xx_dump(struct msm_gpu *gpu);
+static bool a4xx_idle(struct msm_gpu *gpu);
/*
* a4xx_enable_hwcg() - Program the clock control registers
@@ -137,7 +138,7 @@ static bool a4xx_me_init(struct msm_gpu *gpu)
OUT_RING(ring, 0x00000000);
gpu->funcs->flush(gpu);
- return gpu->funcs->idle(gpu);
+ return a4xx_idle(gpu);
}
static int a4xx_hw_init(struct msm_gpu *gpu)
@@ -534,7 +535,6 @@ static int a4xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value)
.last_fence = adreno_last_fence,
.submit = adreno_submit,
.flush = adreno_flush,
- .idle = a4xx_idle,
.irq = a4xx_irq,
.destroy = a4xx_destroy,
#ifdef CONFIG_DEBUG_FS
@@ -282,7 +282,7 @@ static int a5xx_me_init(struct msm_gpu *gpu)
gpu->funcs->flush(gpu);
- return gpu->funcs->idle(gpu) ? 0 : -EINVAL;
+ return a5xx_idle(gpu) ? 0 : -EINVAL;
}
static struct drm_gem_object *a5xx_ucode_load_bo(struct msm_gpu *gpu,
@@ -632,7 +632,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
OUT_RING(gpu->rb, 0x0F);
gpu->funcs->flush(gpu);
- if (!gpu->funcs->idle(gpu))
+ if (!a5xx_idle(gpu))
return -EINVAL;
}
@@ -649,7 +649,7 @@ static int a5xx_hw_init(struct msm_gpu *gpu)
OUT_RING(gpu->rb, 0x00000000);
gpu->funcs->flush(gpu);
- if (!gpu->funcs->idle(gpu))
+ if (!a5xx_idle(gpu))
return -EINVAL;
} else {
/* Print a warning so if we die, we know why */
@@ -726,7 +726,7 @@ static inline bool _a5xx_check_idle(struct msm_gpu *gpu)
A5XX_RBBM_INT_0_MASK_MISC_HANG_DETECT);
}
-static bool a5xx_idle(struct msm_gpu *gpu)
+bool a5xx_idle(struct msm_gpu *gpu)
{
/* wait for CP to drain ringbuffer: */
if (!adreno_idle(gpu))
@@ -1031,7 +1031,6 @@ static void a5xx_show(struct msm_gpu *gpu, struct seq_file *m)
.last_fence = adreno_last_fence,
.submit = a5xx_submit,
.flush = adreno_flush,
- .idle = a5xx_idle,
.irq = a5xx_irq,
.destroy = a5xx_destroy,
#ifdef CONFIG_DEBUG_FS
@@ -58,5 +58,6 @@ static inline int spin_usecs(struct msm_gpu *gpu, uint32_t usecs,
return -ETIMEDOUT;
}
+bool a5xx_idle(struct msm_gpu *gpu);
#endif /* __A5XX_GPU_H__ */
@@ -194,7 +194,7 @@ static int a5xx_gpmu_init(struct msm_gpu *gpu)
gpu->funcs->flush(gpu);
- if (!gpu->funcs->idle(gpu)) {
+ if (!a5xx_idle(gpu)) {
DRM_ERROR("%s: Unable to load GPMU firmware. GPMU will not be active\n",
gpu->name);
return -EINVAL;
@@ -50,7 +50,6 @@ struct msm_gpu_funcs {
void (*submit)(struct msm_gpu *gpu, struct msm_gem_submit *submit,
struct msm_file_private *ctx);
void (*flush)(struct msm_gpu *gpu);
- bool (*idle)(struct msm_gpu *gpu);
irqreturn_t (*irq)(struct msm_gpu *irq);
uint32_t (*last_fence)(struct msm_gpu *gpu);
void (*recover)(struct msm_gpu *gpu);
There isn't any generic code that uses ->idle so remove it. Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org> --- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 4 ++-- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 4 ++-- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 9 ++++----- drivers/gpu/drm/msm/adreno/a5xx_gpu.h | 1 + drivers/gpu/drm/msm/adreno/a5xx_power.c | 2 +- drivers/gpu/drm/msm/msm_gpu.h | 1 - 6 files changed, 10 insertions(+), 11 deletions(-)