From patchwork Tue Nov 21 19:40:57 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 10068839 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 01B166038F for ; Tue, 21 Nov 2017 19:41:39 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DEBC129978 for ; Tue, 21 Nov 2017 19:41:38 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D3BE22997D; Tue, 21 Nov 2017 19:41:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 8202429978 for ; Tue, 21 Nov 2017 19:41:38 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id E07016E5BF; Tue, 21 Nov 2017 19:41:11 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from smtp.codeaurora.org (smtp.codeaurora.org [198.145.29.96]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2B3D36E5A4; Tue, 21 Nov 2017 19:41:07 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 0E4E86084F; Tue, 21 Nov 2017 19:41:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1511293267; bh=3Wlm2c2rrs97unISGDQwcKyI2C9+4W7KT7faursMsqg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=AKX9BMxwGXsNuDI/1EOBxcC0SsP4A2MiPq3ejqVMS4alSV5mL3TDGALlX7oXm/fJi 76Ywb1CiSe+JhMVh0m7a2TpRAtvrp5WecqnEwIdGbpQsPE26LYxXIKZ/KqMcnYjmBU c1WWdwODTGM9zi+yGfLpYQ52QwQXOTZcCQDDTne8= Received: from jcrouse-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 48C6F6081C; Tue, 21 Nov 2017 19:41:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1511293266; bh=3Wlm2c2rrs97unISGDQwcKyI2C9+4W7KT7faursMsqg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=CIhoMo8/mFKo/TlfqX4ntb2uMsFd27SU1wFGs2lcqzc5yImbM6OG8yt1C2gVqLsNF tXJlE1FdrzzcJXmbpGrDFaAv7mfiyfWgPCY1fWRoRIf4LiyCcSP3dv8yBkXK9aPWrZ sPNam/gUo6rL4nQYCtaYVAioqUyf9VD/hwL0EnzA= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 48C6F6081C Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: freedreno@lists.freedesktop.org Subject: [PATCH 7/8] drm/msm/adreno: a5xx: Explicitly program the CP0 performance counter Date: Tue, 21 Nov 2017 12:40:57 -0700 Message-Id: <1511293258-12415-8-git-send-email-jcrouse@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1511293258-12415-1-git-send-email-jcrouse@codeaurora.org> References: <1511293258-12415-1-git-send-email-jcrouse@codeaurora.org> Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Even though the default countable for CP0 is CP_ALWAYS_COUNT (0), program the selector during HW initialization in an effort to be up front about which counters are programmed and why. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 3 +++ 1 file changed, 3 insertions(+) diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index fdbe9e9..56c2c44 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -597,6 +597,9 @@ static int a5xx_hw_init(struct msm_gpu *gpu) /* Turn on performance counters */ gpu_write(gpu, REG_A5XX_RBBM_PERFCTR_CNTL, 0x01); + /* Select CP0 to always count cycles */ + gpu_write(gpu, REG_A5XX_CP_PERFCTR_CP_SEL_0, PERF_CP_ALWAYS_COUNT); + /* Increase VFD cache access so LRZ and other data gets evicted less */ gpu_write(gpu, REG_A5XX_UCHE_CACHE_WAYS, 0x02);