From patchwork Fri Jan 5 18:00:20 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 10146875 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id BE5C6601A1 for ; Fri, 5 Jan 2018 18:00:34 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id AD65723B23 for ; Fri, 5 Jan 2018 18:00:34 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A25B523F88; Fri, 5 Jan 2018 18:00:34 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id EBB8E23B23 for ; Fri, 5 Jan 2018 18:00:33 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D97DD6E3CD; Fri, 5 Jan 2018 18:00:28 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from smtp.codeaurora.org (smtp.codeaurora.org [198.145.29.96]) by gabe.freedesktop.org (Postfix) with ESMTPS id 7C1A86E3C6; Fri, 5 Jan 2018 18:00:27 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 68B4B60B72; Fri, 5 Jan 2018 18:00:27 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1515175227; bh=gZ6hGjD2hidsDPuhKD6mgOA/NtjshXTg9qzFJFQRsa4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=jcwI0p/izuyuYtjIMxQGDEYgge+KanfJZRz07Jr2Izu3d+ogyFl+kLUlHL3RBOqDf +4SdrlrByDKN1yrWGgRlw4ScWz+d2Ch+JQTKjCDhcTHcDPbe0wfaWyqYjgv9fcNTEG HK0arkxQpDNWifBpnjnKmZZeeMh1/vm/AahqlIIM= Received: from jcrouse-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 5A45760B1E; Fri, 5 Jan 2018 18:00:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1515175226; bh=gZ6hGjD2hidsDPuhKD6mgOA/NtjshXTg9qzFJFQRsa4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=V35wjDLwrR2kweTq4+ccThm0CFRYR5gqD8vDBDDZPU9V7KNjgn4zy2pshckgYY4A4 6AioT10ueBV2SmG7QQwsXK4L1QfdZCFFHL6K/g596xP32/baNJlEESJI2IPBRY3gWO HODC8/zaj5YGZ/haop4YVLUctJafGi0wR4pynbIE= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 5A45760B1E Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: freedreno@lists.freedesktop.org Subject: [PATCH 3/4] drm/msm: gpu: Convert the GPU show functions to use the GPU state Date: Fri, 5 Jan 2018 11:00:20 -0700 Message-Id: <1515175221-5601-4-git-send-email-jcrouse@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1515175221-5601-1-git-send-email-jcrouse@codeaurora.org> References: <1515175221-5601-1-git-send-email-jcrouse@codeaurora.org> Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Convert the existing GPU show functions to use the GPU state to dump the information rather than reading it directly from the hardware. This will require an additional step to capture the state before dumping it for the existing nodes but it will greatly facilitate reusing the same code for dumping a previously captured state from a GPU hang. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/adreno/a3xx_gpu.c | 20 ++++++--------- drivers/gpu/drm/msm/adreno/a4xx_gpu.c | 21 ++++++---------- drivers/gpu/drm/msm/adreno/a5xx_gpu.c | 27 ++++++-------------- drivers/gpu/drm/msm/adreno/adreno_gpu.c | 44 ++++++++++++++++----------------- drivers/gpu/drm/msm/adreno/adreno_gpu.h | 9 ++++--- drivers/gpu/drm/msm/msm_debugfs.c | 21 +++++++++++----- drivers/gpu/drm/msm/msm_gpu.h | 3 ++- 7 files changed, 69 insertions(+), 76 deletions(-) diff --git a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c index 5427748..8a7d56ec 100644 --- a/drivers/gpu/drm/msm/adreno/a3xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a3xx_gpu.c @@ -300,9 +300,12 @@ static int a3xx_hw_init(struct msm_gpu *gpu) static void a3xx_recover(struct msm_gpu *gpu) { struct drm_printer p = drm_info_printer(gpu->dev->dev); + struct msm_gpu_state *state; int i; - adreno_show_info(gpu, &p); + state = gpu->funcs->gpu_state_get(gpu); + + adreno_show_info(gpu, state, &p); for (i = 0; i < 8; i++) drm_printf(&p, "CP_SCRATCH_REG%d: %u\n", i, @@ -310,12 +313,14 @@ static void a3xx_recover(struct msm_gpu *gpu) /* dump registers before resetting gpu, if enabled: */ if (hang_debug) - adreno_show_regs(gpu, &p); + adreno_show_regs(gpu, state, &p); gpu_write(gpu, REG_A3XX_RBBM_SW_RESET_CMD, 1); gpu_read(gpu, REG_A3XX_RBBM_SW_RESET_CMD); gpu_write(gpu, REG_A3XX_RBBM_SW_RESET_CMD, 0); adreno_recover(gpu); + + gpu->funcs->gpu_state_put(state); } static void a3xx_destroy(struct msm_gpu *gpu) @@ -409,15 +414,6 @@ static irqreturn_t a3xx_irq(struct msm_gpu *gpu) ~0 /* sentinel */ }; -#ifdef CONFIG_DEBUG_FS -static void a3xx_show(struct msm_gpu *gpu, struct seq_file *m) -{ - seq_printf(m, "status: %08x\n", - gpu_read(gpu, REG_A3XX_RBBM_STATUS)); - adreno_show(gpu, m); -} -#endif - static struct msm_gpu_state *a3xx_gpu_state_get(struct msm_gpu *gpu) { struct msm_gpu_state *state = adreno_gpu_state_get(gpu); @@ -454,7 +450,7 @@ static struct msm_gpu_state *a3xx_gpu_state_get(struct msm_gpu *gpu) .irq = a3xx_irq, .destroy = a3xx_destroy, #ifdef CONFIG_DEBUG_FS - .show = a3xx_show, + .show = adreno_show, #endif .gpu_state_get = a3xx_gpu_state_get, .gpu_state_put = adreno_gpu_state_put, diff --git a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c index 4c66c54..e64c7fc 100644 --- a/drivers/gpu/drm/msm/adreno/a4xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a4xx_gpu.c @@ -298,9 +298,12 @@ static int a4xx_hw_init(struct msm_gpu *gpu) static void a4xx_recover(struct msm_gpu *gpu) { struct drm_printer p = drm_info_printer(gpu->dev->dev); + struct msm_gpu_state *state; int i; - adreno_show_info(gpu, &p); + state = gpu->funcs->gpu_state_get(gpu); + + adreno_show_info(gpu, state, &p); for (i = 0; i < 8; i++) { drm_printf(&p, "CP_SCRATCH_REG%d: %u\n", i, @@ -309,12 +312,14 @@ static void a4xx_recover(struct msm_gpu *gpu) /* dump registers before resetting gpu, if enabled: */ if (hang_debug) - adreno_show_regs(gpu, &p); + adreno_show_regs(gpu, state, &p); gpu_write(gpu, REG_A4XX_RBBM_SW_RESET_CMD, 1); gpu_read(gpu, REG_A4XX_RBBM_SW_RESET_CMD); gpu_write(gpu, REG_A4XX_RBBM_SW_RESET_CMD, 0); adreno_recover(gpu); + + gpu->funcs->gpu_state_put(state); } static void a4xx_destroy(struct msm_gpu *gpu) @@ -454,16 +459,6 @@ static irqreturn_t a4xx_irq(struct msm_gpu *gpu) ~0 /* sentinel */ }; -#ifdef CONFIG_DEBUG_FS -static void a4xx_show(struct msm_gpu *gpu, struct seq_file *m) -{ - seq_printf(m, "status: %08x\n", - gpu_read(gpu, REG_A4XX_RBBM_STATUS)); - adreno_show(gpu, m); - -} -#endif - static struct msm_gpu_state *a4xx_gpu_state_get(struct msm_gpu *gpu) { struct msm_gpu_state *state = adreno_gpu_state_get(gpu); @@ -543,7 +538,7 @@ static int a4xx_get_timestamp(struct msm_gpu *gpu, uint64_t *value) .irq = a4xx_irq, .destroy = a4xx_destroy, #ifdef CONFIG_DEBUG_FS - .show = a4xx_show, + .show = adreno_show, #endif .gpu_state_get = a4xx_gpu_state_get, .gpu_state_put = adreno_gpu_state_put, diff --git a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c index 05046e4..6747b7b 100644 --- a/drivers/gpu/drm/msm/adreno/a5xx_gpu.c +++ b/drivers/gpu/drm/msm/adreno/a5xx_gpu.c @@ -755,21 +755,26 @@ static int a5xx_hw_init(struct msm_gpu *gpu) static void a5xx_recover(struct msm_gpu *gpu) { struct drm_printer p = drm_info_printer(gpu->dev->dev); + struct msm_gpu_state *state; int i; - adreno_show_info(gpu, &p); + state = gpu->funcs->gpu_state_get(gpu); + + adreno_show_info(gpu, state, &p); for (i = 0; i < 8; i++) drm_printf(&p, "CP_SCRATCH_REG%d: %u\n", i, gpu_read(gpu, REG_A5XX_CP_SCRATCH_REG(i))); if (hang_debug) - adreno_show_regs(gpu, &p); + adreno_show_regs(gpu, state, &p); gpu_write(gpu, REG_A5XX_RBBM_SW_RESET_CMD, 1); gpu_read(gpu, REG_A5XX_RBBM_SW_RESET_CMD); gpu_write(gpu, REG_A5XX_RBBM_SW_RESET_CMD, 0); adreno_recover(gpu); + + gpu->funcs->gpu_state_put(state); } static void a5xx_destroy(struct msm_gpu *gpu) @@ -1153,22 +1158,6 @@ static struct msm_gpu_state *a5xx_gpu_state_get(struct msm_gpu *gpu) return state; } -#ifdef CONFIG_DEBUG_FS -static void a5xx_show(struct msm_gpu *gpu, struct seq_file *m) -{ - seq_printf(m, "status: %08x\n", - gpu_read(gpu, REG_A5XX_RBBM_STATUS)); - - /* - * Temporarily disable hardware clock gating before going into - * adreno_show to avoid issues while reading the registers - */ - a5xx_set_hwcg(gpu, false); - adreno_show(gpu, m); - a5xx_set_hwcg(gpu, true); -} -#endif - static struct msm_ringbuffer *a5xx_active_ring(struct msm_gpu *gpu) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); @@ -1190,7 +1179,7 @@ static struct msm_ringbuffer *a5xx_active_ring(struct msm_gpu *gpu) .irq = a5xx_irq, .destroy = a5xx_destroy, #ifdef CONFIG_DEBUG_FS - .show = a5xx_show, + .show = adreno_show, #endif .gpu_state_get = a5xx_gpu_state_get, .gpu_state_put = adreno_gpu_state_put, diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 64da461..ba1b912 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -416,54 +416,54 @@ void adreno_gpu_state_put(struct msm_gpu_state *state) kfree(state); } -void adreno_show_info(struct msm_gpu *gpu, struct drm_printer *p) +void adreno_show_info(struct msm_gpu *gpu, struct msm_gpu_state *state, + struct drm_printer *p) { struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); int i; + if (IS_ERR_OR_NULL(state)) + return; + + drm_printf(p, "status: %08x\n", state->rbbm_status); drm_printf(p, "revision: %d (%d.%d.%d.%d)\n", adreno_gpu->info->revn, adreno_gpu->rev.core, adreno_gpu->rev.major, adreno_gpu->rev.minor, adreno_gpu->rev.patchid); for (i = 0; i < gpu->nr_rings; i++) { - struct msm_ringbuffer *ring = gpu->rb[i]; - drm_printf(p, "rb %d: fence: %d/%d\n", i, - ring->memptrs->fence, ring->seqno); + state->ring[i].fence, state->ring[i].seqno); - drm_printf(p, " rptr: %d\n", - get_rptr(adreno_gpu, ring)); - drm_printf(p, "rb wptr: %d\n", get_wptr(ring)); + drm_printf(p, " rptr: %d\n", state->ring[i].rptr); + drm_printf(p, "rb wptr: %d\n", state->ring[i].wptr); } } -void adreno_show_regs(struct msm_gpu *gpu, struct drm_printer *p) +void adreno_show_regs(struct msm_gpu *gpu, struct msm_gpu_state *state, + struct drm_printer *p) { - struct adreno_gpu *adreno_gpu = to_adreno_gpu(gpu); int i; + if (IS_ERR_OR_NULL(state)) + return; + /* dump these out in a form that can be parsed by demsm: */ drm_printf(p, "IO:region %s 00000000 00020000\n", gpu->name); - for (i = 0; adreno_gpu->registers[i] != ~0; i += 2) { - uint32_t start = adreno_gpu->registers[i]; - uint32_t end = adreno_gpu->registers[i+1]; - uint32_t addr; - - for (addr = start; addr <= end; addr++) { - uint32_t val = gpu_read(gpu, addr); - drm_printf(p, "IO:R %08x %08x\n", addr<<2, val); - } - } + for (i = 0; i < state->nr_registers; i++) + drm_printf(p, "IO:R %08x %08x\n", + state->registers[i * 2] << 2, + state->registers[(i * 2) + 1]); } #ifdef CONFIG_DEBUG_FS -void adreno_show(struct msm_gpu *gpu, struct seq_file *m) +void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, + struct seq_file *m) { struct drm_printer p = drm_seq_file_printer(m); - adreno_show_info(gpu, &p); - adreno_show_regs(gpu, &p); + adreno_show_info(gpu, state, &p); + adreno_show_regs(gpu, state, &p); } #endif diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.h b/drivers/gpu/drm/msm/adreno/adreno_gpu.h index b7c95ee..4542b6b 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.h +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.h @@ -211,7 +211,8 @@ void adreno_submit(struct msm_gpu *gpu, struct msm_gem_submit *submit, void adreno_flush(struct msm_gpu *gpu, struct msm_ringbuffer *ring); bool adreno_idle(struct msm_gpu *gpu, struct msm_ringbuffer *ring); #ifdef CONFIG_DEBUG_FS -void adreno_show(struct msm_gpu *gpu, struct seq_file *m); +void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, + struct seq_file *m); #endif void adreno_dump_info(struct msm_gpu *gpu); void adreno_dump(struct msm_gpu *gpu); @@ -223,8 +224,10 @@ int adreno_gpu_init(struct drm_device *drm, struct platform_device *pdev, int nr_rings); void adreno_gpu_cleanup(struct adreno_gpu *gpu); -void adreno_show_info(struct msm_gpu *gpu, struct drm_printer *p); -void adreno_show_regs(struct msm_gpu *gpu, struct drm_printer *p); +void adreno_show_info(struct msm_gpu *gpu, struct msm_gpu_state *state, + struct drm_printer *p); +void adreno_show_regs(struct msm_gpu *gpu, struct msm_gpu_state *state, + struct drm_printer *p); struct msm_gpu_state *adreno_gpu_state_get(struct msm_gpu *gpu); void adreno_gpu_state_put(struct msm_gpu_state *state); diff --git a/drivers/gpu/drm/msm/msm_debugfs.c b/drivers/gpu/drm/msm/msm_debugfs.c index 1855182..89ee74b 100644 --- a/drivers/gpu/drm/msm/msm_debugfs.c +++ b/drivers/gpu/drm/msm/msm_debugfs.c @@ -25,13 +25,22 @@ static int msm_gpu_show(struct drm_device *dev, struct seq_file *m) { struct msm_drm_private *priv = dev->dev_private; struct msm_gpu *gpu = priv->gpu; + struct msm_gpu_state *state; - if (gpu) { - seq_printf(m, "%s Status:\n", gpu->name); - pm_runtime_get_sync(&gpu->pdev->dev); - gpu->funcs->show(gpu, m); - pm_runtime_put_sync(&gpu->pdev->dev); - } + if (!gpu) + return 0; + + pm_runtime_get_sync(&gpu->pdev->dev); + state = gpu->funcs->gpu_state_get(gpu); + pm_runtime_put_sync(&gpu->pdev->dev); + + if (IS_ERR(state)) + return PTR_ERR(state); + + seq_printf(m, "%s Status:\n", gpu->name); + gpu->funcs->show(gpu, state, m); + + gpu->funcs->gpu_state_put(state); return 0; } diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index d781489..cff52ca 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -65,7 +65,8 @@ struct msm_gpu_funcs { void (*destroy)(struct msm_gpu *gpu); #ifdef CONFIG_DEBUG_FS /* show GPU status in debugfs: */ - void (*show)(struct msm_gpu *gpu, struct seq_file *m); + void (*show)(struct msm_gpu *gpu, struct msm_gpu_state *state, + struct seq_file *m); #endif struct msm_gpu_state *(*gpu_state_get)(struct msm_gpu *gpu); void (*gpu_state_put)(struct msm_gpu_state *state);