From patchwork Thu Feb 8 17:31:56 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 10207549 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id CD453602D8 for ; Thu, 8 Feb 2018 17:32:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BE24929505 for ; Thu, 8 Feb 2018 17:32:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B27922956C; Thu, 8 Feb 2018 17:32:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2F4C429505 for ; Thu, 8 Feb 2018 17:32:47 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D1D7E6E679; Thu, 8 Feb 2018 17:32:18 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from smtp.codeaurora.org (smtp.codeaurora.org [198.145.29.96]) by gabe.freedesktop.org (Postfix) with ESMTPS id 1A48D6E65B; Thu, 8 Feb 2018 17:32:07 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1000) id D44BC607F5; Thu, 8 Feb 2018 17:32:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1518111126; bh=KraQdIiA3mCBE01ZMtwWizFpR/YZeeKWS3aWeFVCnd4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FJ8tsnShfqPkhPBg5hA12m7NG+2nVyGs1Sji0VjJkOxcqkqTgCACH6ttIQ4I/9Xk9 R+h+uSXfyEjYHE3bRwE1UvOCGHqoBbsl3pHmeWsySLLmFoYSoOc4IGRjX2+zwsFavG MGHK3lZjPqm2a1geRGXU7IOYmp0aj3j45pUL8BBg= Received: from jcrouse-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id B5A25607F5; Thu, 8 Feb 2018 17:32:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1518111126; bh=KraQdIiA3mCBE01ZMtwWizFpR/YZeeKWS3aWeFVCnd4=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=FJ8tsnShfqPkhPBg5hA12m7NG+2nVyGs1Sji0VjJkOxcqkqTgCACH6ttIQ4I/9Xk9 R+h+uSXfyEjYHE3bRwE1UvOCGHqoBbsl3pHmeWsySLLmFoYSoOc4IGRjX2+zwsFavG MGHK3lZjPqm2a1geRGXU7IOYmp0aj3j45pUL8BBg= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org B5A25607F5 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org From: Jordan Crouse To: freedreno@lists.freedesktop.org Subject: [PATCH 7/8] drm/msm/adreno: Add ringbuffer data to the GPU state Date: Thu, 8 Feb 2018 10:31:56 -0700 Message-Id: <1518111117-7408-8-git-send-email-jcrouse@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1518111117-7408-1-git-send-email-jcrouse@codeaurora.org> References: <1518111117-7408-1-git-send-email-jcrouse@codeaurora.org> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Add the contents of each ringbuffer to the GPU state and dump the data in the crash file encoded with ascii85. To save space only the used portions of the ringbuffer are dumped. Signed-off-by: Jordan Crouse --- Documentation/gpu/drm-msm-crash-dump.txt | 5 ++++ drivers/gpu/drm/msm/adreno/adreno_gpu.c | 40 ++++++++++++++++++++++++++++++++ drivers/gpu/drm/msm/msm_gpu.h | 2 ++ 3 files changed, 47 insertions(+) diff --git a/Documentation/gpu/drm-msm-crash-dump.txt b/Documentation/gpu/drm-msm-crash-dump.txt index ec56640..3f54b44 100644 --- a/Documentation/gpu/drm-msm-crash-dump.txt +++ b/Documentation/gpu/drm-msm-crash-dump.txt @@ -22,6 +22,11 @@ ringbuffer: # Ringbuffer data. There will be a sequence for each ringbuffer retired-fence: # [decimal] THe last fence retired on the ring rptr: # [decimal] The current read pointer (rptr) for the ring wptr: # [decimal] The current write pointer (wptr) for the ring + size: # [decimal] The maximum size of the ring programmed in the + # hardware + data: # [ascii85] The contents of the ring encoded as ascii85. + # Only the unused portions of the ring will be printed (up + # to a maximum of 'size' bytes registers: # Sets of register values. This section can be used multiple # times for different ranges of registers. Each register will be # on its own line. diff --git a/drivers/gpu/drm/msm/adreno/adreno_gpu.c b/drivers/gpu/drm/msm/adreno/adreno_gpu.c index 920db2e..e9b7b36 100644 --- a/drivers/gpu/drm/msm/adreno/adreno_gpu.c +++ b/drivers/gpu/drm/msm/adreno/adreno_gpu.c @@ -17,6 +17,7 @@ * this program. If not, see . */ +#include #include #include "adreno_gpu.h" #include "msm_gem.h" @@ -397,10 +398,29 @@ struct msm_gpu_state *adreno_gpu_state_get(struct msm_gpu *gpu) do_gettimeofday(&state->time); for (i = 0; i < gpu->nr_rings; i++) { + int size = 0, j; + state->ring[i].fence = gpu->rb[i]->memptrs->fence; state->ring[i].seqno = gpu->rb[i]->seqno; state->ring[i].rptr = get_rptr(adreno_gpu, gpu->rb[i]); state->ring[i].wptr = get_wptr(gpu->rb[i]); + + /* + * Only copy used parts of the ring buffers (this should save + * data size for lightly used rings) + */ + for(j = 0; j < MSM_GPU_RINGBUFFER_SZ >> 2; j++) + if (gpu->rb[i]->start[j]) + size = j; + + if (size) { + state->ring[i].data = kmalloc((size + 1) << 2, GFP_KERNEL); + if (state->ring[i].data) { + memcpy(state->ring[i].data, gpu->rb[i]->start, + (size + 1) << 2); + state->ring[i].data_size = (size + 1) << 2; + } + } } /* Count the number of registers */ @@ -431,9 +451,13 @@ struct msm_gpu_state *adreno_gpu_state_get(struct msm_gpu *gpu) static void adreno_gpu_state_destroy(struct kref *kref) { + int i; struct msm_gpu_state *state = container_of(kref, struct msm_gpu_state, ref); + for(i = 0; i < ARRAY_SIZE(state->ring); i++) + kfree(state->ring[i].data); + kfree(state->comm); kfree(state->cmd); kfree(state->registers); @@ -473,6 +497,22 @@ void adreno_show(struct msm_gpu *gpu, struct msm_gpu_state *state, drm_printf(p, " retired-fence: %d\n", state->ring[i].fence); drm_printf(p, " rptr: %d\n", state->ring[i].rptr); drm_printf(p, " wptr: %d\n", state->ring[i].wptr); + drm_printf(p, " size: %d\n", MSM_GPU_RINGBUFFER_SZ); + + if (state->ring[i].data && state->ring[i].data_size) { + u32 *ptr = (u32 *) state->ring[i].data; + char out[ASCII85_BUFSZ]; + long len = ascii85_encode_len(state->ring[i].data_size); + int j; + + drm_printf(p, " data: !!ascii85 |\n"); + drm_printf(p, " "); + + for(j = 0; j < len; j++) + drm_printf(p, ascii85_encode(ptr[j], out)); + + drm_printf(p, "\n"); + } } drm_printf(p, "registers:\n"); diff --git a/drivers/gpu/drm/msm/msm_gpu.h b/drivers/gpu/drm/msm/msm_gpu.h index e65f507..48f7b21 100644 --- a/drivers/gpu/drm/msm/msm_gpu.h +++ b/drivers/gpu/drm/msm/msm_gpu.h @@ -190,6 +190,8 @@ struct msm_gpu_state { u32 seqno; u32 rptr; u32 wptr; + void *data; + int data_size; } ring[MSM_GPU_MAX_RINGS]; int nr_registers;