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[6/6] drm/msm/A6xx: Enable L1 preemption level

Message ID 1520489185-21828-7-git-send-email-smasetty@codeaurora.org (mailing list archive)
State New, archived
Headers show

Commit Message

Sharat Masetty March 8, 2018, 6:06 a.m. UTC 
This patch enables L1 level which is a finer grained preemption
at either a draw call or a bin boundary. The worst case switching
latency is higher in this case but that is a trade off we make for
enabling faster preemption.

Signed-off-by: Sharat Masetty <smasetty@codeaurora.org>
---
 drivers/gpu/drm/msm/adreno/a6xx_preempt.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)
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Patch

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_preempt.c b/drivers/gpu/drm/msm/adreno/a6xx_preempt.c
index 0d2b612..4e83a4f 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_preempt.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_preempt.c
@@ -301,9 +301,17 @@  void a6xx_preempt_init(struct msm_gpu *gpu)
 	}
 
 	/* TODO: make this configurable? */
-	a6xx_gpu->preempt_level = 0;
+	/*
+	 * Use L1 preemption level which is preemption at either the draw call
+	 * level or the bin boundary level
+	 */
+	a6xx_gpu->preempt_level = 1;
 	a6xx_gpu->uses_gmem = 1;
-	a6xx_gpu->skip_save_restore = 0;
+	/*
+	 * Skip CP save and restore when preempting between bins, use
+	 * this only when the preemption level is 1
+	 */
+	a6xx_gpu->skip_save_restore = 1;
 
 	a6xx_gpu->scratch_ptr  = msm_gem_kernel_new(gpu->dev,
 			gpu->nr_rings * sizeof(uint64_t), MSM_BO_WC,