From patchwork Fri Mar 23 07:19:48 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sharat Masetty X-Patchwork-Id: 10302781 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 7CBA4600F6 for ; Fri, 23 Mar 2018 07:20:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 6758628C55 for ; Fri, 23 Mar 2018 07:20:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 5BFD828C5D; Fri, 23 Mar 2018 07:20:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 2208E28C55 for ; Fri, 23 Mar 2018 07:20:36 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id CED7B6E2D0; Fri, 23 Mar 2018 07:20:33 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from smtp.codeaurora.org (smtp.codeaurora.org [198.145.29.96]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0BA336E272; Fri, 23 Mar 2018 07:20:33 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1000) id E2EE66085F; Fri, 23 Mar 2018 07:20:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521789632; bh=6wXUKZjtVxlsl3+GwrDc20jdqYLml9LX0e4QHcthoY8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nf/GboVZ6TbHI2drUdnmwPpu3GV7mC7cGfZosuGTuN24giigwc3JL+33HQJB0FHcO BMSZXJUBVazU3X81Ryp3irfiJ8pc5avR0v1XeFyX00cABV7Waxmy0lzPVmqKHfHWp7 CZ/7p/hR4I95obsJNfzokcf2vuVZWlDy079wFsSQ= Received: from smasetty-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: smasetty@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id F2BBC60C54; Fri, 23 Mar 2018 07:20:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1521789632; bh=6wXUKZjtVxlsl3+GwrDc20jdqYLml9LX0e4QHcthoY8=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=nf/GboVZ6TbHI2drUdnmwPpu3GV7mC7cGfZosuGTuN24giigwc3JL+33HQJB0FHcO BMSZXJUBVazU3X81Ryp3irfiJ8pc5avR0v1XeFyX00cABV7Waxmy0lzPVmqKHfHWp7 CZ/7p/hR4I95obsJNfzokcf2vuVZWlDy079wFsSQ= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org F2BBC60C54 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=smasetty@codeaurora.org From: Sharat Masetty To: freedreno@lists.freedesktop.org Subject: [PATCH 2/5] arm64:dts:sdm845: Add support for GPU LLCC Date: Fri, 23 Mar 2018 12:49:48 +0530 Message-Id: <1521789591-28628-3-git-send-email-smasetty@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1521789591-28628-1-git-send-email-smasetty@codeaurora.org> References: <1521789591-28628-1-git-send-email-smasetty@codeaurora.org> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: linux-arm-msm@vger.kernel.org, Sharat Masetty , dri-devel@lists.freedesktop.org MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Add client side bindings required for the GPU to use the last level system cache. Also add a register range in the GPU CX domain. Signed-off-by: Sharat Masetty Reviewed-by: Jordan Crouse --- arch/arm64/boot/dts/qcom/sdm845.dtsi | 8 ++++++-- 1 file changed, 6 insertions(+), 2 deletions(-) diff --git a/arch/arm64/boot/dts/qcom/sdm845.dtsi b/arch/arm64/boot/dts/qcom/sdm845.dtsi index eb0a1b2..7e2d938 100644 --- a/arch/arm64/boot/dts/qcom/sdm845.dtsi +++ b/arch/arm64/boot/dts/qcom/sdm845.dtsi @@ -887,8 +887,8 @@ compatible = "qcom,adreno-630.2", "qcom,adreno"; #stream-id-cells = <16>; - reg = <0x5000000 0x40000>; - reg-names = "kgsl_3d0_reg_memory"; + reg = <0x5000000 0x40000>, <0x509e000 0x10>; + reg-names = "kgsl_3d0_reg_memory", "cx_mem"; /* * Look ma, no clocks! The GPU clocks and power are controlled @@ -898,6 +898,10 @@ interrupts = <0 300 0>; interrupt-names = "kgsl_3d0_irq"; + /* GPU related llc slices */ + cache-slice-names = "gpu", "gpuhtw"; + cache-slices = <&llcc 12>, <&llcc 11>; + iommus = <&kgsl_smmu 0>; operating-points-v2 = <&gpu_opp_table>;