| Message ID | 1523384703-17621-1-git-send-email-ayan.halder@arm.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Tue, Apr 10, 2018 at 07:25:03PM +0100, Ayan Kumar Halder wrote: > On some Mali-DP processors, the LAYER_FORMAT register contains fields > other than the format. These bits were unconditionally cleared when > setting the pixel format, whereas they should be preserved at their > reset values. > > Reported-by: Brian Starkey <brian.starkey@arm.com> > Reported-by: Liviu Dudau <liviu.dudau@arm.com> > Signed-off-by: Ayan Kumar halder <ayan.halder@arm.com> Acked-by: Liviu Dudau <liviu.dudau@arm.com> Thanks for catching this in testing! Best regards, Liviu > --- > drivers/gpu/drm/arm/malidp_planes.c | 5 ++++- > 1 file changed, 4 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/arm/malidp_planes.c b/drivers/gpu/drm/arm/malidp_planes.c > index 7a44897..4af3c1f 100644 > --- a/drivers/gpu/drm/arm/malidp_planes.c > +++ b/drivers/gpu/drm/arm/malidp_planes.c > @@ -23,6 +23,7 @@ > > /* Layer specific register offsets */ > #define MALIDP_LAYER_FORMAT 0x000 > +#define LAYER_FORMAT_MASK 0x3f > #define MALIDP_LAYER_CONTROL 0x004 > #define LAYER_ENABLE (1 << 0) > #define LAYER_FLOWCFG_MASK 7 > @@ -337,7 +338,9 @@ static void malidp_de_plane_update(struct drm_plane *plane, > dest_w = plane->state->crtc_w; > dest_h = plane->state->crtc_h; > > - malidp_hw_write(mp->hwdev, ms->format, mp->layer->base); > + val = malidp_hw_read(mp->hwdev, mp->layer->base); > + val = (val & ~LAYER_FORMAT_MASK) | ms->format; > + malidp_hw_write(mp->hwdev, val, mp->layer->base); > > for (i = 0; i < ms->n_planes; i++) { > /* calculate the offset for the layer's plane registers */ > -- > 2.7.4 >
diff --git a/drivers/gpu/drm/arm/malidp_planes.c b/drivers/gpu/drm/arm/malidp_planes.c index 7a44897..4af3c1f 100644 --- a/drivers/gpu/drm/arm/malidp_planes.c +++ b/drivers/gpu/drm/arm/malidp_planes.c @@ -23,6 +23,7 @@ /* Layer specific register offsets */ #define MALIDP_LAYER_FORMAT 0x000 +#define LAYER_FORMAT_MASK 0x3f #define MALIDP_LAYER_CONTROL 0x004 #define LAYER_ENABLE (1 << 0) #define LAYER_FLOWCFG_MASK 7 @@ -337,7 +338,9 @@ static void malidp_de_plane_update(struct drm_plane *plane, dest_w = plane->state->crtc_w; dest_h = plane->state->crtc_h; - malidp_hw_write(mp->hwdev, ms->format, mp->layer->base); + val = malidp_hw_read(mp->hwdev, mp->layer->base); + val = (val & ~LAYER_FORMAT_MASK) | ms->format; + malidp_hw_write(mp->hwdev, val, mp->layer->base); for (i = 0; i < ms->n_planes; i++) { /* calculate the offset for the layer's plane registers */
On some Mali-DP processors, the LAYER_FORMAT register contains fields other than the format. These bits were unconditionally cleared when setting the pixel format, whereas they should be preserved at their reset values. Reported-by: Brian Starkey <brian.starkey@arm.com> Reported-by: Liviu Dudau <liviu.dudau@arm.com> Signed-off-by: Ayan Kumar halder <ayan.halder@arm.com> --- drivers/gpu/drm/arm/malidp_planes.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)