From patchwork Wed Apr 11 20:49:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Stefan Schake X-Patchwork-Id: 10337303 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id E17786020F for ; Wed, 11 Apr 2018 20:49:44 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id D158926E54 for ; Wed, 11 Apr 2018 20:49:44 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id C5ED527FB1; Wed, 11 Apr 2018 20:49:44 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.1 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, DKIM_SIGNED, FREEMAIL_FROM, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED, T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 719AB26E54 for ; Wed, 11 Apr 2018 20:49:44 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 23A766E720; Wed, 11 Apr 2018 20:49:41 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-wr0-x244.google.com (mail-wr0-x244.google.com [IPv6:2a00:1450:400c:c0c::244]) by gabe.freedesktop.org (Postfix) with ESMTPS id D63B66E703 for ; Wed, 11 Apr 2018 20:49:38 +0000 (UTC) Received: by mail-wr0-x244.google.com with SMTP id z73so3033919wrb.0 for ; Wed, 11 Apr 2018 13:49:38 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=gmail.com; s=20161025; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=ShylTkef4Ic2FKgar3wviEIhSbS+vS2XkMqn1HNKNHM=; b=iChdBtd3mwvv/HIoJE90nLGOjOYYrIySWFtvQ8OIUBPsTQwH0LLOkIxOJR16aHxRAW kk0kPjpaWUgdK2ergjfAt+kh1fGpSSBSyAvs3I0boKUS9d9ezyMTwn0sfhTiCuZONvKS I4yyyWnq43zjHXCmwtEKtXbjIOCfv0JXaUKTE7FzbFU4ImX7/t3hvhC8vl39GVwKIMME XG45w5licY6lefnIzrHV3lnB+70O/CCO/WsG0FtB8FBAqONF5f1RphY3IKLldrGZ6FX/ PMQxxXTseQlUNMZq2bGqINd9QDxT3fQLJ+q0fK/QndQWEFvEetYdAyXC4ptFVrkF+Plc mQcg== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=ShylTkef4Ic2FKgar3wviEIhSbS+vS2XkMqn1HNKNHM=; b=GDXinfxv35SKiU6GUbIw3YN+n0IcmcTlCmbapy9Mlj4SAVAaGFy36YKmtkOygGzOY/ oWClQhvXSXfIhYEHD8s5h+Qc9WeOaiq6035p66R9Ij9BnsQDxPzp1DTBfEY3D5DVHS8k VsK5M7A86pIvxPSRzbcZp3068xr5QcjnAB9fMOPLyVKjor5Sf6UKMvpaQCOlQhFvyio9 0VDuwpa6Ll+WOE9o0lXOAiwoQZQwCawDGGwJQeVDsBy/l/GvAqb5ux7EPFZZacTRYwtW u6iRLAkbBYTzozJprZ4jtRxEM14sYSm64p4Czrb1goIvBZVfTD0YMxCQQNGvJXXGkiw6 6ZwA== X-Gm-Message-State: ALQs6tADM69i/lyUCZCD6LZzAKGpgoWTGud8WMC1zcLIi675SsGDWLXu qpwF1YqqRSHWTxOmsBY9O8U= X-Google-Smtp-Source: AIpwx48p5WdVCwmyViWHB6wWVe8smRRhY+Giy478MuEVwbWjKTTJN+PjrlaQzsrBFOJoTTYjNfMjGw== X-Received: by 10.223.187.138 with SMTP id q10mr4121102wrg.62.1523479777413; Wed, 11 Apr 2018 13:49:37 -0700 (PDT) Received: from localhost.localdomain (x4db52ef0.dyn.telefonica.de. [77.181.46.240]) by smtp.gmail.com with ESMTPSA id 10sm2710816wrz.58.2018.04.11.13.49.35 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Wed, 11 Apr 2018 13:49:36 -0700 (PDT) From: Stefan Schake To: eric@anholt.net Subject: [PATCH v3 3/4] drm/vc4: Move CRTC state to header Date: Wed, 11 Apr 2018 22:49:14 +0200 Message-Id: <1523479755-20812-4-git-send-email-stschake@gmail.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1523479755-20812-1-git-send-email-stschake@gmail.com> References: <1523479755-20812-1-git-send-email-stschake@gmail.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: airlied@linux.ie, linux-rpi-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, Stefan Schake MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP We need to access the channel for configuring our CTM hardware. Signed-off-by: Stefan Schake --- v3: New in the series drivers/gpu/drm/vc4/vc4_crtc.c | 33 --------------------------------- drivers/gpu/drm/vc4/vc4_drv.h | 33 +++++++++++++++++++++++++++++++++ 2 files changed, 33 insertions(+), 33 deletions(-) diff --git a/drivers/gpu/drm/vc4/vc4_crtc.c b/drivers/gpu/drm/vc4/vc4_crtc.c index 285f88d..08fe8dd 100644 --- a/drivers/gpu/drm/vc4/vc4_crtc.c +++ b/drivers/gpu/drm/vc4/vc4_crtc.c @@ -42,51 +42,18 @@ #include "vc4_drv.h" #include "vc4_regs.h" -struct vc4_crtc { - struct drm_crtc base; - const struct vc4_crtc_data *data; - void __iomem *regs; - - /* Timestamp at start of vblank irq - unaffected by lock delays. */ - ktime_t t_vblank; - - /* Which HVS channel we're using for our CRTC. */ - int channel; - - u8 lut_r[256]; - u8 lut_g[256]; - u8 lut_b[256]; - /* Size in pixels of the COB memory allocated to this CRTC. */ - u32 cob_size; - - struct drm_pending_vblank_event *event; -}; - struct vc4_crtc_state { struct drm_crtc_state base; /* Dlist area for this CRTC configuration. */ struct drm_mm_node mm; }; -static inline struct vc4_crtc * -to_vc4_crtc(struct drm_crtc *crtc) -{ - return (struct vc4_crtc *)crtc; -} - static inline struct vc4_crtc_state * to_vc4_crtc_state(struct drm_crtc_state *crtc_state) { return (struct vc4_crtc_state *)crtc_state; } -struct vc4_crtc_data { - /* Which channel of the HVS this pixelvalve sources from. */ - int hvs_channel; - - enum vc4_encoder_type encoder_types[4]; -}; - #define CRTC_WRITE(offset, val) writel(val, vc4_crtc->regs + (offset)) #define CRTC_READ(offset) readl(vc4_crtc->regs + (offset)) diff --git a/drivers/gpu/drm/vc4/vc4_drv.h b/drivers/gpu/drm/vc4/vc4_drv.h index 1b4cd1f..4288615 100644 --- a/drivers/gpu/drm/vc4/vc4_drv.h +++ b/drivers/gpu/drm/vc4/vc4_drv.h @@ -392,6 +392,39 @@ to_vc4_encoder(struct drm_encoder *encoder) return container_of(encoder, struct vc4_encoder, base); } +struct vc4_crtc_data { + /* Which channel of the HVS this pixelvalve sources from. */ + int hvs_channel; + + enum vc4_encoder_type encoder_types[4]; +}; + +struct vc4_crtc { + struct drm_crtc base; + const struct vc4_crtc_data *data; + void __iomem *regs; + + /* Timestamp at start of vblank irq - unaffected by lock delays. */ + ktime_t t_vblank; + + /* Which HVS channel we're using for our CRTC. */ + int channel; + + u8 lut_r[256]; + u8 lut_g[256]; + u8 lut_b[256]; + /* Size in pixels of the COB memory allocated to this CRTC. */ + u32 cob_size; + + struct drm_pending_vblank_event *event; +}; + +static inline struct vc4_crtc * +to_vc4_crtc(struct drm_crtc *crtc) +{ + return (struct vc4_crtc *)crtc; +} + #define V3D_READ(offset) readl(vc4->v3d->regs + offset) #define V3D_WRITE(offset, val) writel(val, vc4->v3d->regs + offset) #define HVS_READ(offset) readl(vc4->hvs->regs + offset)