@@ -64,7 +64,6 @@ msm-y := \
disp/dpu1/dpu_hw_color_processing_v1_7.o \
disp/dpu1/dpu_hw_ctl.o \
disp/dpu1/dpu_hw_ds.o \
- disp/dpu1/dpu_hw_dsc.o \
disp/dpu1/dpu_hw_dspp.o \
disp/dpu1/dpu_hw_interrupts.o \
disp/dpu1/dpu_hw_intf.o \
@@ -39,12 +39,8 @@
static const struct drm_prop_enum_list e_topology_name[] = {
{DPU_RM_TOPOLOGY_NONE, "dpu_none"},
{DPU_RM_TOPOLOGY_SINGLEPIPE, "dpu_singlepipe"},
- {DPU_RM_TOPOLOGY_SINGLEPIPE_DSC, "dpu_singlepipe_dsc"},
{DPU_RM_TOPOLOGY_DUALPIPE, "dpu_dualpipe"},
- {DPU_RM_TOPOLOGY_DUALPIPE_DSC, "dpu_dualpipe_dsc"},
{DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE, "dpu_dualpipemerge"},
- {DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC, "dpu_dualpipemerge_dsc"},
- {DPU_RM_TOPOLOGY_DUALPIPE_DSCMERGE, "dpu_dualpipe_dscmerge"},
{DPU_RM_TOPOLOGY_PPSPLIT, "dpu_ppsplit"},
};
static const struct drm_prop_enum_list e_topology_control[] = {
@@ -147,7 +147,7 @@ struct dpu_crtc_event {
* @num_ctls : Number of ctl paths in use
* @num_mixers : Number of mixers in use
* @mixers_swapped: Whether the mixers have been swapped for left/right update
- * especially in the case of DSC Merge.
+ especially in the case of DSC Merge.
* @mixers : List of active mixers
* @event : Pointer to last received drm vblank event. If there is a
* pending vblank event, this will be non-null.
@@ -32,7 +32,6 @@
#include "dpu_formats.h"
#include "dpu_encoder_phys.h"
#include "dpu_power_handle.h"
-#include "dpu_hw_dsc.h"
#include "dpu_crtc.h"
#include "dpu_trace.h"
#include "dpu_core_irq.h"
@@ -152,7 +151,6 @@ enum dpu_enc_rc_states {
* Only valid after enable. Cleared as disable.
* @hw_pp Handle to the pingpong blocks used for the display. No.
* pingpong blocks can be different than num_phys_encs.
- * @hw_dsc: Array of DSC block handles used for the display.
* @intfs_swapped Whether or not the phys_enc interfaces have been swapped
* for partial update right-only cases, such as pingpong
* split where virtual pingpong does not generate IRQs
@@ -199,7 +197,6 @@ struct dpu_encoder_virt {
struct dpu_encoder_phys *phys_encs[MAX_PHYS_ENCODERS_PER_VIRTUAL];
struct dpu_encoder_phys *cur_master;
struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
- struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC];
bool intfs_swapped;
@@ -234,21 +231,6 @@ struct dpu_encoder_virt {
#define to_dpu_encoder_virt(x) container_of(x, struct dpu_encoder_virt, base)
-bool dpu_encoder_is_dsc_enabled(struct drm_encoder *drm_enc)
-
-{
- struct dpu_encoder_virt *dpu_enc;
- struct msm_compression_info *comp_info;
-
- if (!drm_enc)
- return false;
-
- dpu_enc = to_dpu_encoder_virt(drm_enc);
- comp_info = &dpu_enc->mode_info.comp_info;
-
- return (comp_info->comp_type == MSM_DISPLAY_COMPRESSION_DSC);
-}
-
void dpu_encoder_set_idle_timeout(struct drm_encoder *drm_enc, u32 idle_timeout)
{
struct dpu_encoder_virt *dpu_enc;
@@ -260,30 +242,6 @@ void dpu_encoder_set_idle_timeout(struct drm_encoder *drm_enc, u32 idle_timeout)
dpu_enc->idle_timeout = idle_timeout;
}
-bool dpu_encoder_is_dsc_merge(struct drm_encoder *drm_enc)
-{
- enum dpu_rm_topology_name topology;
- struct dpu_encoder_virt *dpu_enc;
- struct drm_connector *drm_conn;
-
- if (!drm_enc)
- return false;
-
- dpu_enc = to_dpu_encoder_virt(drm_enc);
- if (!dpu_enc->cur_master)
- return false;
-
- drm_conn = dpu_enc->cur_master->connector;
- if (!drm_conn)
- return false;
-
- topology = dpu_connector_get_topology_name(drm_conn);
- if (topology == DPU_RM_TOPOLOGY_DUALPIPE_DSCMERGE)
- return true;
-
- return false;
-}
-
static inline int _dpu_encoder_power_enable(struct dpu_encoder_virt *dpu_enc,
bool enable)
{
@@ -745,312 +703,6 @@ static int dpu_encoder_virt_atomic_check(
return ret;
}
-static int _dpu_encoder_dsc_update_pic_dim(struct msm_display_dsc_info *dsc,
- int pic_width, int pic_height)
-{
- if (!dsc || !pic_width || !pic_height) {
- DPU_ERROR("invalid input: pic_width=%d pic_height=%d\n",
- pic_width, pic_height);
- return -EINVAL;
- }
-
- if ((pic_width % dsc->slice_width) ||
- (pic_height % dsc->slice_height)) {
- DPU_ERROR("pic_dim=%dx%d has to be multiple of slice=%dx%d\n",
- pic_width, pic_height,
- dsc->slice_width, dsc->slice_height);
- return -EINVAL;
- }
-
- dsc->pic_width = pic_width;
- dsc->pic_height = pic_height;
-
- return 0;
-}
-
-static void _dpu_encoder_dsc_pclk_param_calc(struct msm_display_dsc_info *dsc,
- int intf_width)
-{
- int slice_per_pkt, slice_per_intf;
- int bytes_in_slice, total_bytes_per_intf;
-
- if (!dsc || !dsc->slice_width || !dsc->slice_per_pkt ||
- (intf_width < dsc->slice_width)) {
- DPU_ERROR("invalid input: intf_width=%d slice_width=%d\n",
- intf_width, dsc ? dsc->slice_width : -1);
- return;
- }
-
- slice_per_pkt = dsc->slice_per_pkt;
- slice_per_intf = DIV_ROUND_UP(intf_width, dsc->slice_width);
-
- /*
- * If slice_per_pkt is greater than slice_per_intf then default to 1.
- * This can happen during partial update.
- */
- if (slice_per_pkt > slice_per_intf)
- slice_per_pkt = 1;
-
- bytes_in_slice = DIV_ROUND_UP(dsc->slice_width * dsc->bpp, 8);
- total_bytes_per_intf = bytes_in_slice * slice_per_intf;
-
- dsc->eol_byte_num = total_bytes_per_intf % 3;
- dsc->pclk_per_line = DIV_ROUND_UP(total_bytes_per_intf, 3);
- dsc->bytes_in_slice = bytes_in_slice;
- dsc->bytes_per_pkt = bytes_in_slice * slice_per_pkt;
- dsc->pkt_per_line = slice_per_intf / slice_per_pkt;
-}
-
-static int _dpu_encoder_dsc_initial_line_calc(struct msm_display_dsc_info *dsc,
- int enc_ip_width)
-{
- int ssm_delay, total_pixels, soft_slice_per_enc;
-
- soft_slice_per_enc = enc_ip_width / dsc->slice_width;
-
- /*
- * minimum number of initial line pixels is a sum of:
- * 1. sub-stream multiplexer delay (83 groups for 8bpc,
- * 91 for 10 bpc) * 3
- * 2. for two soft slice cases, add extra sub-stream multiplexer * 3
- * 3. the initial xmit delay
- * 4. total pipeline delay through the "lock step" of encoder (47)
- * 5. 6 additional pixels as the output of the rate buffer is
- * 48 bits wide
- */
- ssm_delay = ((dsc->bpc < 10) ? 84 : 92);
- total_pixels = ssm_delay * 3 + dsc->initial_xmit_delay + 47;
- if (soft_slice_per_enc > 1)
- total_pixels += (ssm_delay * 3);
- dsc->initial_lines = DIV_ROUND_UP(total_pixels, dsc->slice_width);
- return 0;
-}
-
-static bool _dpu_encoder_dsc_ich_reset_override_needed(bool pu_en,
- struct msm_display_dsc_info *dsc)
-{
- /*
- * As per the DSC spec, ICH_RESET can be either end of the slice line
- * or at the end of the slice. HW internally generates ich_reset at
- * end of the slice line if DSC_MERGE is used or encoder has two
- * soft slices. However, if encoder has only 1 soft slice and DSC_MERGE
- * is not used then it will generate ich_reset at the end of slice.
- *
- * Now as per the spec, during one PPS session, position where
- * ich_reset is generated should not change. Now if full-screen frame
- * has more than 1 soft slice then HW will automatically generate
- * ich_reset at the end of slice_line. But for the same panel, if
- * partial frame is enabled and only 1 encoder is used with 1 slice,
- * then HW will generate ich_reset at end of the slice. This is a
- * mismatch. Prevent this by overriding HW's decision.
- */
- return pu_en && dsc && (dsc->full_frame_slices > 1) &&
- (dsc->slice_width == dsc->pic_width);
-}
-
-static void _dpu_encoder_dsc_pipe_cfg(struct dpu_hw_dsc *hw_dsc,
- struct dpu_hw_pingpong *hw_pp, struct msm_display_dsc_info *dsc,
- u32 common_mode, bool ich_reset)
-{
- if (hw_dsc->ops.dsc_config)
- hw_dsc->ops.dsc_config(hw_dsc, dsc, common_mode, ich_reset);
-
- if (hw_dsc->ops.dsc_config_thresh)
- hw_dsc->ops.dsc_config_thresh(hw_dsc, dsc);
-
- if (hw_pp->ops.setup_dsc)
- hw_pp->ops.setup_dsc(hw_pp);
-
- if (hw_pp->ops.enable_dsc)
- hw_pp->ops.enable_dsc(hw_pp);
-}
-
-static int _dpu_encoder_dsc_n_lm_1_enc_1_intf(struct dpu_encoder_virt *dpu_enc)
-{
- int this_frame_slices;
- int intf_ip_w, enc_ip_w;
- int ich_res, dsc_common_mode = 0;
- int rc = 0;
-
- struct dpu_hw_pingpong *hw_pp = dpu_enc->hw_pp[0];
- struct dpu_hw_dsc *hw_dsc = dpu_enc->hw_dsc[0];
- struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
- struct msm_display_dsc_info *dsc =
- &dpu_enc->mode_info.comp_info.dsc_info;
-
- rc = _dpu_encoder_dsc_update_pic_dim(dsc, dsc->pic_width,
- dsc->pic_height);
- if (rc) {
- DPU_ERROR_ENC(dpu_enc, "failed to update DSC pic dim\n");
- return rc;
- }
-
- this_frame_slices = dsc->pic_width / dsc->slice_width;
- intf_ip_w = this_frame_slices * dsc->slice_width;
- _dpu_encoder_dsc_pclk_param_calc(dsc, intf_ip_w);
-
- enc_ip_w = intf_ip_w;
- _dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w);
-
- ich_res = _dpu_encoder_dsc_ich_reset_override_needed(false, dsc);
-
- if (enc_master->intf_mode == INTF_MODE_VIDEO)
- dsc_common_mode = DSC_MODE_VIDEO;
-
- DPU_DEBUG_ENC(dpu_enc, "pic_w: %d pic_h: %d mode:%d\n",
- dsc->pic_width, dsc->pic_height, dsc_common_mode);
- DPU_EVT32(DRMID(&dpu_enc->base), dsc->pic_width, dsc->pic_height,
- dsc_common_mode);
-
- _dpu_encoder_dsc_pipe_cfg(hw_dsc, hw_pp, dsc, dsc_common_mode,
- ich_res);
-
- return 0;
-}
-static int _dpu_encoder_dsc_2_lm_2_enc_2_intf(struct dpu_encoder_virt *dpu_enc)
-{
- int this_frame_slices;
- int intf_ip_w, enc_ip_w;
- int ich_res, dsc_common_mode;
- int rc = 0;
-
- struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
- struct dpu_hw_dsc *l_hw_dsc = dpu_enc->hw_dsc[0];
- struct dpu_hw_dsc *r_hw_dsc = dpu_enc->hw_dsc[1];
- struct dpu_hw_pingpong *l_hw_pp = dpu_enc->hw_pp[0];
- struct dpu_hw_pingpong *r_hw_pp = dpu_enc->hw_pp[1];
- struct msm_display_dsc_info *dsc =
- &dpu_enc->mode_info.comp_info.dsc_info;
-
- rc = _dpu_encoder_dsc_update_pic_dim(dsc,
- dsc->pic_width * dpu_enc->display_num_of_h_tiles,
- dsc->pic_height);
- if (rc) {
- DPU_ERROR_ENC(dpu_enc, "failed to update DSC pic dim\n");
- return rc;
- }
-
-
- this_frame_slices = dsc->pic_width / dsc->slice_width;
- intf_ip_w = this_frame_slices * dsc->slice_width;
-
- intf_ip_w /= 2;
- _dpu_encoder_dsc_pclk_param_calc(dsc, intf_ip_w);
-
- enc_ip_w = intf_ip_w;
- _dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w);
-
- ich_res = _dpu_encoder_dsc_ich_reset_override_needed(false, dsc);
-
- dsc_common_mode = DSC_MODE_SPLIT_PANEL;
- if (enc_master->intf_mode == INTF_MODE_VIDEO)
- dsc_common_mode |= DSC_MODE_VIDEO;
-
- DPU_DEBUG_ENC(dpu_enc, "pic_w: %d pic_h: %d mode:%d\n",
- dsc->pic_width, dsc->pic_height, dsc_common_mode);
- DPU_EVT32(DRMID(&dpu_enc->base), dsc->pic_width, dsc->pic_height,
- dsc_common_mode);
-
- _dpu_encoder_dsc_pipe_cfg(l_hw_dsc, l_hw_pp, dsc, dsc_common_mode,
- ich_res);
- _dpu_encoder_dsc_pipe_cfg(r_hw_dsc, r_hw_pp, dsc, dsc_common_mode,
- ich_res);
-
- return 0;
-}
-
-static int _dpu_encoder_dsc_2_lm_2_enc_1_intf(struct dpu_encoder_virt *dpu_enc)
-{
- int this_frame_slices;
- int intf_ip_w, enc_ip_w;
- int ich_res, dsc_common_mode;
- int rc = 0;
-
- struct dpu_encoder_phys *enc_master = dpu_enc->cur_master;
- struct dpu_hw_dsc *l_hw_dsc = dpu_enc->hw_dsc[0];
- struct dpu_hw_dsc *r_hw_dsc = dpu_enc->hw_dsc[1];
- struct dpu_hw_pingpong *l_hw_pp = dpu_enc->hw_pp[0];
- struct dpu_hw_pingpong *r_hw_pp = dpu_enc->hw_pp[1];
- struct msm_display_dsc_info *dsc =
- &dpu_enc->mode_info.comp_info.dsc_info;
-
- rc = _dpu_encoder_dsc_update_pic_dim(dsc, dsc->pic_width,
- dsc->pic_height);
- if (rc) {
- DPU_ERROR_ENC(dpu_enc, "failed to update DSC pic dim\n");
- return rc;
- }
-
- this_frame_slices = dsc->pic_width / dsc->slice_width;
- intf_ip_w = this_frame_slices * dsc->slice_width;
- _dpu_encoder_dsc_pclk_param_calc(dsc, intf_ip_w);
-
- /*
- * when using 2 encoders for the same stream, no. of slices
- * need to be same on both the encoders.
- */
- enc_ip_w = intf_ip_w / 2;
- _dpu_encoder_dsc_initial_line_calc(dsc, enc_ip_w);
-
- ich_res = _dpu_encoder_dsc_ich_reset_override_needed(false, dsc);
-
- dsc_common_mode = DSC_MODE_MULTIPLEX | DSC_MODE_SPLIT_PANEL;
- if (enc_master->intf_mode == INTF_MODE_VIDEO)
- dsc_common_mode |= DSC_MODE_VIDEO;
-
- DPU_DEBUG_ENC(dpu_enc, "pic_w: %d pic_h: %d mode:%d\n",
- dsc->pic_width, dsc->pic_height, dsc_common_mode);
- DPU_EVT32(DRMID(&dpu_enc->base), dsc->pic_width, dsc->pic_height,
- dsc_common_mode);
-
- _dpu_encoder_dsc_pipe_cfg(l_hw_dsc, l_hw_pp, dsc, dsc_common_mode,
- ich_res);
- _dpu_encoder_dsc_pipe_cfg(r_hw_dsc, r_hw_pp, dsc, dsc_common_mode,
- ich_res);
-
- return 0;
-}
-
-static int _dpu_encoder_dsc_setup(struct dpu_encoder_virt *dpu_enc)
-{
- enum dpu_rm_topology_name topology;
- struct drm_connector *drm_conn;
- int ret = 0;
-
- if (!dpu_enc)
- return -EINVAL;
-
- drm_conn = dpu_enc->phys_encs[0]->connector;
-
- topology = dpu_connector_get_topology_name(drm_conn);
- if (topology == DPU_RM_TOPOLOGY_NONE) {
- DPU_ERROR_ENC(dpu_enc, "topology not set yet\n");
- return -EINVAL;
- }
-
- DPU_DEBUG_ENC(dpu_enc, "topology:%d\n", topology);
- DPU_EVT32(DRMID(&dpu_enc->base));
-
- switch (topology) {
- case DPU_RM_TOPOLOGY_SINGLEPIPE_DSC:
- case DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC:
- ret = _dpu_encoder_dsc_n_lm_1_enc_1_intf(dpu_enc);
- break;
- case DPU_RM_TOPOLOGY_DUALPIPE_DSCMERGE:
- ret = _dpu_encoder_dsc_2_lm_2_enc_1_intf(dpu_enc);
- break;
- case DPU_RM_TOPOLOGY_DUALPIPE_DSC:
- ret = _dpu_encoder_dsc_2_lm_2_enc_2_intf(dpu_enc);
- break;
- default:
- DPU_ERROR_ENC(dpu_enc, "No DSC support for topology %d",
- topology);
- return -EINVAL;
- };
-
- return ret;
-}
-
static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc,
struct msm_display_info *disp_info)
{
@@ -1109,102 +761,8 @@ static void _dpu_encoder_update_vsync_source(struct dpu_encoder_virt *dpu_enc,
hw_mdptop->ops.setup_vsync_source(hw_mdptop, &vsync_cfg);
}
-}
-
-static int _dpu_encoder_dsc_disable(struct dpu_encoder_virt *dpu_enc)
-{
- enum dpu_rm_topology_name topology;
- struct drm_connector *drm_conn;
- int i, ret = 0;
- struct dpu_hw_pingpong *hw_pp[MAX_CHANNELS_PER_ENC];
- struct dpu_hw_dsc *hw_dsc[MAX_CHANNELS_PER_ENC] = {NULL};
- int pp_count = 0;
- int dsc_count = 0;
-
- if (!dpu_enc || !dpu_enc->phys_encs[0] ||
- !dpu_enc->phys_encs[0]->connector) {
- DPU_ERROR("invalid params %d %d\n",
- !dpu_enc, dpu_enc ? !dpu_enc->phys_encs[0] : -1);
- return -EINVAL;
- }
-
- drm_conn = dpu_enc->phys_encs[0]->connector;
-
- topology = dpu_connector_get_topology_name(drm_conn);
- if (topology == DPU_RM_TOPOLOGY_NONE) {
- DPU_ERROR_ENC(dpu_enc, "topology not set yet\n");
- return -EINVAL;
- }
-
- switch (topology) {
- case DPU_RM_TOPOLOGY_SINGLEPIPE:
- case DPU_RM_TOPOLOGY_SINGLEPIPE_DSC:
- /* single PP */
- hw_pp[0] = dpu_enc->hw_pp[0];
- hw_dsc[0] = dpu_enc->hw_dsc[0];
- pp_count = 1;
- dsc_count = 1;
- break;
- case DPU_RM_TOPOLOGY_DUALPIPE_DSC:
- case DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC:
- case DPU_RM_TOPOLOGY_DUALPIPE_DSCMERGE:
- /* dual dsc */
- for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
- hw_dsc[i] = dpu_enc->hw_dsc[i];
- if (hw_dsc[i])
- dsc_count++;
- }
- /* fall through */
- case DPU_RM_TOPOLOGY_DUALPIPE:
- case DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE:
- /* dual pp */
- for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
- hw_pp[i] = dpu_enc->hw_pp[i];
- if (hw_pp[i])
- pp_count++;
- }
- break;
- default:
- DPU_DEBUG_ENC(dpu_enc, "Unexpected topology:%d\n", topology);
- return -EINVAL;
- };
-
- DPU_EVT32(DRMID(&dpu_enc->base), topology, pp_count, dsc_count);
-
- if (pp_count > MAX_CHANNELS_PER_ENC ||
- dsc_count > MAX_CHANNELS_PER_ENC) {
- DPU_ERROR_ENC(dpu_enc, "Wrong count pp:%d dsc:%d top:%d\n",
- pp_count, dsc_count, topology);
- return -EINVAL;
- }
-
- /* Disable DSC for all the pp's present in this topology */
- for (i = 0; i < pp_count; i++) {
-
- if (!hw_pp[i]) {
- DPU_ERROR_ENC(dpu_enc, "null pp:%d top:%d cnt:%d\n",
- i, topology, pp_count);
- return -EINVAL;
- }
-
- if (hw_pp[i]->ops.disable_dsc)
- hw_pp[i]->ops.disable_dsc(hw_pp[i]);
- }
-
- /* Disable DSC HW */
- for (i = 0; i < dsc_count; i++) {
-
- if (!hw_dsc[i]) {
- DPU_ERROR_ENC(dpu_enc, "null dsc:%d top:%d cnt:%d\n",
- i, topology, dsc_count);
- return -EINVAL;
- }
-
- if (hw_dsc[i]->ops.dsc_disable)
- hw_dsc[i]->ops.dsc_disable(hw_dsc[i]);
- }
- return ret;
+ return;
}
static void _dpu_encoder_irq_control(struct drm_encoder *drm_enc, bool enable)
@@ -1607,7 +1165,7 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
struct list_head *connector_list;
struct drm_connector *conn = NULL, *conn_iter;
struct dpu_connector *dpu_conn = NULL;
- struct dpu_rm_hw_iter dsc_iter, pp_iter;
+ struct dpu_rm_hw_iter pp_iter;
int i = 0, ret;
if (!drm_enc) {
@@ -1658,12 +1216,6 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
ret);
return;
}
-
- /*
- * Disable dsc before switch the mode and after pre_modeset,
- * to guarantee that previous kickoff finished.
- */
- _dpu_encoder_dsc_disable(dpu_enc);
}
/* Reserve dynamic resources now. Indicating non-AtomicTest phase */
@@ -1683,14 +1235,6 @@ static void dpu_encoder_virt_mode_set(struct drm_encoder *drm_enc,
dpu_enc->hw_pp[i] = (struct dpu_hw_pingpong *) pp_iter.hw;
}
- dpu_rm_init_hw_iter(&dsc_iter, drm_enc->base.id, DPU_HW_BLK_DSC);
- for (i = 0; i < MAX_CHANNELS_PER_ENC; i++) {
- dpu_enc->hw_dsc[i] = NULL;
- if (!dpu_rm_get_hw(&dpu_kms->rm, &dsc_iter))
- break;
- dpu_enc->hw_dsc[i] = (struct dpu_hw_dsc *) dsc_iter.hw;
- }
-
for (i = 0; i < dpu_enc->num_phys_encs; i++) {
struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
@@ -1782,7 +1326,6 @@ static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
{
struct dpu_encoder_virt *dpu_enc = NULL;
int i, ret = 0;
- struct msm_compression_info *comp_info = NULL;
struct drm_display_mode *cur_mode = NULL;
if (!drm_enc) {
@@ -1790,7 +1333,6 @@ static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
return;
}
dpu_enc = to_dpu_encoder_virt(drm_enc);
- comp_info = &dpu_enc->mode_info.comp_info;
cur_mode = &dpu_enc->base.crtc->state->adjusted_mode;
DPU_DEBUG_ENC(dpu_enc, "\n");
@@ -1825,7 +1367,6 @@ static void dpu_encoder_virt_enable(struct drm_encoder *drm_enc)
if (!phys)
continue;
- phys->comp_type = comp_info->comp_type;
if (phys != dpu_enc->cur_master) {
/**
* on DMS request, the encoder will be enabled
@@ -1900,13 +1441,6 @@ static void dpu_encoder_virt_disable(struct drm_encoder *drm_enc)
phys->ops.disable(phys);
}
- /*
- * disable dsc after the transfer is complete (for command mode)
- * and after physical encoder is disabled, to make sure timing
- * engine is already disabled (for video mode).
- */
- _dpu_encoder_dsc_disable(dpu_enc);
-
/* after phys waits for frame-done, should be no more frames pending */
if (atomic_xchg(&dpu_enc->frame_done_timeout, 0)) {
DPU_ERROR("enc%d timeout pending\n", drm_enc->base.id);
@@ -2742,12 +2276,6 @@ void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc,
dpu_enc->cur_master->connector->base.id,
rc);
}
-
- if (dpu_encoder_is_dsc_enabled(drm_enc)) {
- rc = _dpu_encoder_dsc_setup(dpu_enc);
- if (rc)
- DPU_ERROR_ENC(dpu_enc, "failed to setup DSC: %d\n", rc);
- }
}
void dpu_encoder_kickoff(struct drm_encoder *drm_enc)
@@ -145,20 +145,6 @@ int dpu_encoder_wait_for_event(struct drm_encoder *drm_encoder,
void dpu_encoder_virt_restore(struct drm_encoder *encoder);
/**
- * dpu_encoder_is_dsc_enabled - check if encoder is in DSC mode
- * @drm_enc: Pointer to drm encoder object
- * @Return: true if encoder is in DSC mode
- */
-bool dpu_encoder_is_dsc_enabled(struct drm_encoder *drm_enc);
-
-/**
- * dpu_encoder_is_dsc_merge - check if encoder is in DSC merge mode
- * @drm_enc: Pointer to drm encoder object
- * @Return: true if encoder is in DSC merge mode
- */
-bool dpu_encoder_is_dsc_merge(struct drm_encoder *drm_enc);
-
-/**
* dpu_encoder_check_mode - check if given mode is supported or not
* @drm_enc: Pointer to drm encoder object
* @mode: Mode to be checked
@@ -232,7 +232,6 @@ struct dpu_encoder_irq {
* @split_role: Role to play in a split-panel configuration
* @intf_mode: Interface mode
* @intf_idx: Interface index on dpu hardware
- * @comp_type: Type of compression supported
* @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes
* @enable_state: Enable state tracking
* @vblank_refcount: Reference count of vblank request
@@ -262,7 +261,6 @@ struct dpu_encoder_phys {
enum dpu_enc_split_role split_role;
enum dpu_intf_mode intf_mode;
enum dpu_intf intf_idx;
- enum msm_display_compression_type comp_type;
spinlock_t *enc_spinlock;
enum dpu_enc_enable_state enable_state;
atomic_t vblank_refcount;
@@ -384,7 +382,6 @@ struct dpu_encoder_phys_wb {
* @split_role: Role to play in a split-panel configuration
* @intf_idx: Interface index this phys_enc will control
* @wb_idx: Writeback index this phys_enc will control
- * @comp_type: Type of compression supported
* @enc_spinlock: Virtual-Encoder-Wide Spin Lock for IRQ purposes
*/
struct dpu_enc_phys_init_params {
@@ -394,7 +391,6 @@ struct dpu_enc_phys_init_params {
enum dpu_enc_split_role split_role;
enum dpu_intf intf_idx;
enum dpu_wb wb_idx;
- enum msm_display_compression_type comp_type;
spinlock_t *enc_spinlock;
};
@@ -479,8 +475,7 @@ static inline enum dpu_3d_blend_mode dpu_encoder_helper_get_3d_blend_mode(
topology = dpu_connector_get_topology_name(phys_enc->connector);
if (phys_enc->split_role == ENC_ROLE_SOLO &&
- (topology == DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE ||
- topology == DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC))
+ topology == DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE)
return BLEND_3D_H_ROW_INT;
return BLEND_3D_NONE;
@@ -1237,7 +1237,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init(
phys_enc->enc_spinlock = p->enc_spinlock;
cmd_enc->stream_sel = 0;
phys_enc->enable_state = DPU_ENC_DISABLED;
- phys_enc->comp_type = p->comp_type;
for (i = 0; i < INTR_IDX_MAX; i++) {
irq = &phys_enc->irq[i];
INIT_LIST_HEAD(&irq->cb.list);
@@ -77,9 +77,6 @@ static void drm_mode_to_intf_timing_params(
* <---------------------------- [hv]total ------------->
*/
timing->width = mode->hdisplay; /* active width */
- if (vid_enc->base.comp_type == MSM_DISPLAY_COMPRESSION_DSC)
- timing->width = DIV_ROUND_UP(timing->width, 3);
-
timing->height = mode->vdisplay; /* active height */
timing->xres = timing->width;
timing->yres = timing->height;
@@ -379,8 +376,7 @@ static bool _dpu_encoder_phys_is_dual_ctl(struct dpu_encoder_phys *phys_enc)
return false;
topology = dpu_connector_get_topology_name(phys_enc->connector);
- if ((topology == DPU_RM_TOPOLOGY_DUALPIPE_DSC) ||
- (topology == DPU_RM_TOPOLOGY_DUALPIPE))
+ if (topology == DPU_RM_TOPOLOGY_DUALPIPE)
return true;
return false;
@@ -915,7 +911,6 @@ struct dpu_encoder_phys *dpu_encoder_phys_vid_init(
phys_enc->split_role = p->split_role;
phys_enc->intf_mode = INTF_MODE_VIDEO;
phys_enc->enc_spinlock = p->enc_spinlock;
- phys_enc->comp_type = p->comp_type;
for (i = 0; i < INTR_IDX_MAX; i++) {
irq = &phys_enc->irq[i];
INIT_LIST_HEAD(&irq->cb.list);
@@ -380,29 +380,6 @@
};
/*************************************************************
- * DSC sub blocks config
- *************************************************************/
-
-static struct dpu_dsc_cfg sdm845_dsc[] = {
- {
- .name = "dsc_0", .id = DSC_0,
- .base = 0x81000, .len = 0x140
- },
- {
- .name = "dsc_1", .id = DSC_1,
- .base = 0x81400, .len = 0x140
- },
- {
- .name = "dsc_2", .id = DSC_2,
- .base = 0x81800, .len = 0x140
- },
- {
- .name = "dsc_3", .id = DSC_3,
- .base = 0x81c00, .len = 0x140
- },
-};
-
-/*************************************************************
* INTF sub blocks config
*************************************************************/
#define INTF_BLK(_name, _id, _base, _type, _ctrl_id) \
@@ -591,8 +568,6 @@ void sdm845_cfg_init(struct dpu_mdss_cfg *dpu_cfg)
.ds = sdm845_ds,
.pingpong_count = ARRAY_SIZE(sdm845_pp),
.pingpong = sdm845_pp,
- .dsc_count = ARRAY_SIZE(sdm845_dsc),
- .dsc = sdm845_dsc,
.cdm_count = ARRAY_SIZE(sdm845_cdm),
.cdm = sdm845_cdm,
.intf_count = ARRAY_SIZE(sdm845_intf),
@@ -199,7 +199,6 @@ enum {
* @DPU_PINGPONG_TE2 Additional tear check block for split pipes
* @DPU_PINGPONG_SPLIT PP block supports split fifo
* @DPU_PINGPONG_SLAVE PP block is a suitable slave for split fifo
- * @DPU_PINGPONG_DSC, Display stream compression blocks
* @DPU_PINGPONG_DITHER, Dither blocks
* @DPU_PINGPONG_MAX
*/
@@ -208,7 +207,6 @@ enum {
DPU_PINGPONG_TE2,
DPU_PINGPONG_SPLIT,
DPU_PINGPONG_SLAVE,
- DPU_PINGPONG_DSC,
DPU_PINGPONG_DITHER,
DPU_PINGPONG_MAX
};
@@ -489,7 +487,6 @@ struct dpu_dspp_sub_blks {
struct dpu_pingpong_sub_blks {
struct dpu_pp_blk te;
struct dpu_pp_blk te2;
- struct dpu_pp_blk dsc;
struct dpu_pp_blk dither;
};
@@ -671,16 +668,6 @@ struct dpu_pingpong_cfg {
};
/**
- * struct dpu_dsc_cfg - information of DSC blocks
- * @id enum identifying this block
- * @base register offset of this block
- * @features bit mask identifying sub-blocks/features
- */
-struct dpu_dsc_cfg {
- DPU_HW_BLK_INFO;
-};
-
-/**
* struct dpu_cdm_cfg - information of chroma down blocks
* @id enum identifying this block
* @base register offset of this block
@@ -916,9 +903,6 @@ struct dpu_mdss_cfg {
u32 pingpong_count;
struct dpu_pingpong_cfg *pingpong;
- u32 dsc_count;
- struct dpu_dsc_cfg *dsc;
-
u32 cdm_count;
struct dpu_cdm_cfg *cdm;
deleted file mode 100644
@@ -1,252 +0,0 @@
-/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#include "dpu_hw_mdss.h"
-#include "dpu_hwio.h"
-#include "dpu_hw_catalog.h"
-#include "dpu_hw_dsc.h"
-#include "dpu_hw_pingpong.h"
-#include "dpu_dbg.h"
-#include "dpu_kms.h"
-
-#define DSC_COMMON_MODE 0x000
-#define DSC_ENC 0X004
-#define DSC_PICTURE 0x008
-#define DSC_SLICE 0x00C
-#define DSC_CHUNK_SIZE 0x010
-#define DSC_DELAY 0x014
-#define DSC_SCALE_INITIAL 0x018
-#define DSC_SCALE_DEC_INTERVAL 0x01C
-#define DSC_SCALE_INC_INTERVAL 0x020
-#define DSC_FIRST_LINE_BPG_OFFSET 0x024
-#define DSC_BPG_OFFSET 0x028
-#define DSC_DSC_OFFSET 0x02C
-#define DSC_FLATNESS 0x030
-#define DSC_RC_MODEL_SIZE 0x034
-#define DSC_RC 0x038
-#define DSC_RC_BUF_THRESH 0x03C
-#define DSC_RANGE_MIN_QP 0x074
-#define DSC_RANGE_MAX_QP 0x0B0
-#define DSC_RANGE_BPG_OFFSET 0x0EC
-
-static void dpu_hw_dsc_disable(struct dpu_hw_dsc *dsc)
-{
- struct dpu_hw_blk_reg_map *dsc_c = &dsc->hw;
-
- DPU_REG_WRITE(dsc_c, DSC_COMMON_MODE, 0);
-}
-
-static void dpu_hw_dsc_config(struct dpu_hw_dsc *hw_dsc,
- struct msm_display_dsc_info *dsc, u32 mode,
- bool ich_reset_override)
-{
- u32 data;
- int bpp, lsb;
- u32 initial_lines = dsc->initial_lines;
- bool is_cmd_mode = !(mode & BIT(2));
- struct dpu_hw_blk_reg_map *dsc_c = &hw_dsc->hw;
-
- DPU_REG_WRITE(dsc_c, DSC_COMMON_MODE, mode);
-
- data = 0;
- if (ich_reset_override)
- data = 3 << 28;
-
- if (is_cmd_mode)
- initial_lines += 1;
-
- data |= (initial_lines << 20);
- data |= ((dsc->slice_last_group_size - 1) << 18);
- /* bpp is 6.4 format, 4 LSBs bits are for fractional part */
- lsb = dsc->bpp % 4;
- bpp = dsc->bpp / 4;
- bpp *= 4; /* either 8 or 12 */
- bpp <<= 4;
- bpp |= lsb;
- data |= (bpp << 8);
- data |= (dsc->block_pred_enable << 7);
- data |= (dsc->line_buf_depth << 3);
- data |= (dsc->enable_422 << 2);
- data |= (dsc->convert_rgb << 1);
- data |= dsc->input_10_bits;
-
- DPU_REG_WRITE(dsc_c, DSC_ENC, data);
-
- data = dsc->pic_width << 16;
- data |= dsc->pic_height;
- DPU_REG_WRITE(dsc_c, DSC_PICTURE, data);
-
- data = dsc->slice_width << 16;
- data |= dsc->slice_height;
- DPU_REG_WRITE(dsc_c, DSC_SLICE, data);
-
- data = dsc->chunk_size << 16;
- DPU_REG_WRITE(dsc_c, DSC_CHUNK_SIZE, data);
-
- data = dsc->initial_dec_delay << 16;
- data |= dsc->initial_xmit_delay;
- DPU_REG_WRITE(dsc_c, DSC_DELAY, data);
-
- data = dsc->initial_scale_value;
- DPU_REG_WRITE(dsc_c, DSC_SCALE_INITIAL, data);
-
- data = dsc->scale_decrement_interval;
- DPU_REG_WRITE(dsc_c, DSC_SCALE_DEC_INTERVAL, data);
-
- data = dsc->scale_increment_interval;
- DPU_REG_WRITE(dsc_c, DSC_SCALE_INC_INTERVAL, data);
-
- data = dsc->first_line_bpg_offset;
- DPU_REG_WRITE(dsc_c, DSC_FIRST_LINE_BPG_OFFSET, data);
-
- data = dsc->nfl_bpg_offset << 16;
- data |= dsc->slice_bpg_offset;
- DPU_REG_WRITE(dsc_c, DSC_BPG_OFFSET, data);
-
- data = dsc->initial_offset << 16;
- data |= dsc->final_offset;
- DPU_REG_WRITE(dsc_c, DSC_DSC_OFFSET, data);
-
- data = dsc->det_thresh_flatness << 10;
- data |= dsc->max_qp_flatness << 5;
- data |= dsc->min_qp_flatness;
- DPU_REG_WRITE(dsc_c, DSC_FLATNESS, data);
-
- data = dsc->rc_model_size;
- DPU_REG_WRITE(dsc_c, DSC_RC_MODEL_SIZE, data);
-
- data = dsc->tgt_offset_lo << 18;
- data |= dsc->tgt_offset_hi << 14;
- data |= dsc->quant_incr_limit1 << 9;
- data |= dsc->quant_incr_limit0 << 4;
- data |= dsc->edge_factor;
- DPU_REG_WRITE(dsc_c, DSC_RC, data);
-}
-
-static void dpu_hw_dsc_config_thresh(struct dpu_hw_dsc *hw_dsc,
- struct msm_display_dsc_info *dsc)
-{
- u32 *lp;
- char *cp;
- int i;
-
- struct dpu_hw_blk_reg_map *dsc_c = &hw_dsc->hw;
- u32 off = 0x0;
-
- lp = dsc->buf_thresh;
- off = DSC_RC_BUF_THRESH;
- for (i = 0; i < 14; i++) {
- DPU_REG_WRITE(dsc_c, off, *lp++);
- off += 4;
- }
-
- cp = dsc->range_min_qp;
- off = DSC_RANGE_MIN_QP;
- for (i = 0; i < 15; i++) {
- DPU_REG_WRITE(dsc_c, off, *cp++);
- off += 4;
- }
-
- cp = dsc->range_max_qp;
- off = DSC_RANGE_MAX_QP;
- for (i = 0; i < 15; i++) {
- DPU_REG_WRITE(dsc_c, off, *cp++);
- off += 4;
- }
-
- cp = dsc->range_bpg_offset;
- off = DSC_RANGE_BPG_OFFSET;
- for (i = 0; i < 15; i++) {
- DPU_REG_WRITE(dsc_c, off, *cp++);
- off += 4;
- }
-}
-
-static struct dpu_dsc_cfg *_dsc_offset(enum dpu_dsc dsc,
- struct dpu_mdss_cfg *m,
- void __iomem *addr,
- struct dpu_hw_blk_reg_map *b)
-{
- int i;
-
- for (i = 0; i < m->dsc_count; i++) {
- if (dsc == m->dsc[i].id) {
- b->base_off = addr;
- b->blk_off = m->dsc[i].base;
- b->length = m->dsc[i].len;
- b->hwversion = m->hwversion;
- b->log_mask = DPU_DBG_MASK_DSC;
- return &m->dsc[i];
- }
- }
-
- return NULL;
-}
-
-static void _setup_dsc_ops(struct dpu_hw_dsc_ops *ops,
- unsigned long cap)
-{
- ops->dsc_disable = dpu_hw_dsc_disable;
- ops->dsc_config = dpu_hw_dsc_config;
- ops->dsc_config_thresh = dpu_hw_dsc_config_thresh;
-};
-
-static struct dpu_hw_blk_ops dpu_hw_ops = {
- .start = NULL,
- .stop = NULL,
-};
-
-struct dpu_hw_dsc *dpu_hw_dsc_init(enum dpu_dsc idx,
- void __iomem *addr,
- struct dpu_mdss_cfg *m)
-{
- struct dpu_hw_dsc *c;
- struct dpu_dsc_cfg *cfg;
- int rc;
-
- c = kzalloc(sizeof(*c), GFP_KERNEL);
- if (!c)
- return ERR_PTR(-ENOMEM);
-
- cfg = _dsc_offset(idx, m, addr, &c->hw);
- if (IS_ERR_OR_NULL(cfg)) {
- kfree(c);
- return ERR_PTR(-EINVAL);
- }
-
- c->idx = idx;
- c->caps = cfg;
- _setup_dsc_ops(&c->ops, c->caps->features);
-
- rc = dpu_hw_blk_init(&c->base, DPU_HW_BLK_DSC, idx, &dpu_hw_ops);
- if (rc) {
- DPU_ERROR("failed to init hw blk %d\n", rc);
- goto blk_init_error;
- }
-
- dpu_dbg_reg_register_dump_range(DPU_DBG_NAME, cfg->name, c->hw.blk_off,
- c->hw.blk_off + c->hw.length, c->hw.xin_id);
-
- return c;
-
-blk_init_error:
- kzfree(c);
-
- return ERR_PTR(rc);
-}
-
-void dpu_hw_dsc_destroy(struct dpu_hw_dsc *dsc)
-{
- if (dsc)
- dpu_hw_blk_destroy(&dsc->base);
- kfree(dsc);
-}
deleted file mode 100644
@@ -1,100 +0,0 @@
-/* Copyright (c) 2017-2018, The Linux Foundation. All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License version 2 and
- * only version 2 as published by the Free Software Foundation.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- * GNU General Public License for more details.
- */
-
-#ifndef _DPU_HW_DSC_H
-#define _DPU_HW_DSC_H
-
-#include "dpu_hw_catalog.h"
-#include "dpu_hw_mdss.h"
-#include "dpu_hw_util.h"
-#include "dpu_hw_blk.h"
-
-struct dpu_hw_dsc;
-struct msm_display_dsc_info;
-
-#define DSC_MODE_SPLIT_PANEL BIT(0)
-#define DSC_MODE_MULTIPLEX BIT(1)
-#define DSC_MODE_VIDEO BIT(2)
-
-/**
- * struct dpu_hw_dsc_ops - interface to the dsc hardware driver functions
- * Assumption is these functions will be called after clocks are enabled
- */
-struct dpu_hw_dsc_ops {
- /**
- * dsc_disable - disable dsc
- * @hw_dsc: Pointer to dsc context
- */
- void (*dsc_disable)(struct dpu_hw_dsc *hw_dsc);
-
- /**
- * dsc_config - configures dsc encoder
- * @hw_dsc: Pointer to dsc context
- * @dsc: panel dsc parameters
- * @mode: dsc topology mode to be set
- * @ich_reset_override: option to reset ich
- */
- void (*dsc_config)(struct dpu_hw_dsc *hw_dsc,
- struct msm_display_dsc_info *dsc,
- u32 mode, bool ich_reset_override);
-
- /**
- * dsc_config_thresh - programs panel thresholds
- * @hw_dsc: Pointer to dsc context
- * @dsc: panel dsc parameters
- */
- void (*dsc_config_thresh)(struct dpu_hw_dsc *hw_dsc,
- struct msm_display_dsc_info *dsc);
-};
-
-struct dpu_hw_dsc {
- struct dpu_hw_blk base;
- struct dpu_hw_blk_reg_map hw;
-
- /* dsc */
- enum dpu_dsc idx;
- const struct dpu_dsc_cfg *caps;
-
- /* ops */
- struct dpu_hw_dsc_ops ops;
-};
-
-/**
- * dpu_hw_dsc - convert base object dpu_hw_base to container
- * @hw: Pointer to base hardware block
- * return: Pointer to hardware block container
- */
-static inline struct dpu_hw_dsc *to_dpu_hw_dsc(struct dpu_hw_blk *hw)
-{
- return container_of(hw, struct dpu_hw_dsc, base);
-}
-
-/**
- * dpu_hw_dsc_init - initializes the dsc block for the passed
- * dsc idx.
- * @idx: DSC index for which driver object is required
- * @addr: Mapped register io address of MDP
- * @m: Pointer to mdss catalog data
- * Returns: Error code or allocated dpu_hw_dsc context
- */
-struct dpu_hw_dsc *dpu_hw_dsc_init(enum dpu_dsc idx,
- void __iomem *addr,
- struct dpu_mdss_cfg *m);
-
-/**
- * dpu_hw_dsc_destroy - destroys dsc driver context
- * should be called to free the context
- * @dsc: Pointer to dsc driver context returned by dpu_hw_dsc_init
- */
-void dpu_hw_dsc_destroy(struct dpu_hw_dsc *dsc);
-
-#endif /*_DPU_HW_DSC_H */
@@ -106,7 +106,6 @@ enum dpu_hw_blk_type {
DPU_HW_BLK_PINGPONG,
DPU_HW_BLK_INTF,
DPU_HW_BLK_WB,
- DPU_HW_BLK_DSC,
DPU_HW_BLK_MAX,
};
@@ -208,17 +207,6 @@ enum dpu_pingpong {
PINGPONG_MAX
};
-enum dpu_dsc {
- DSC_NONE = 0,
- DSC_0,
- DSC_1,
- DSC_2,
- DSC_3,
- DSC_4,
- DSC_5,
- DSC_MAX
-};
-
enum dpu_intf {
INTF_0 = 1,
INTF_1,
@@ -482,9 +470,8 @@ struct dpu_mdss_color {
#define DPU_DBG_MASK_WB (1 << 8)
#define DPU_DBG_MASK_TOP (1 << 9)
#define DPU_DBG_MASK_VBIF (1 << 10)
-#define DPU_DBG_MASK_DSC (1 << 11)
-#define DPU_DBG_MASK_ROT (1 << 12)
-#define DPU_DBG_MASK_DS (1 << 13)
+#define DPU_DBG_MASK_ROT (1 << 11)
+#define DPU_DBG_MASK_DS (1 << 12)
/**
* struct dpu_hw_cp_cfg: hardware dspp/lm feature payload.
@@ -36,9 +36,6 @@
#define PP_FBC_MODE 0x034
#define PP_FBC_BUDGET_CTL 0x038
#define PP_FBC_LOSSY_MODE 0x03C
-#define PP_DSC_MODE 0x0a0
-#define PP_DCE_DATA_IN_SWAP 0x0ac
-#define PP_DCE_DATA_OUT_SWAP 0x0c8
#define DITHER_DEPTH_MAP_INDEX 9
static u32 dither_depth_map[DITHER_DEPTH_MAP_INDEX] = {
@@ -151,48 +148,6 @@ static int dpu_hw_pp_poll_timeout_wr_ptr(struct dpu_hw_pingpong *pp,
return rc;
}
-static void dpu_hw_pp_dsc_enable(struct dpu_hw_pingpong *pp)
-{
- struct dpu_hw_blk_reg_map *c;
-
- if (!pp)
- return;
- c = &pp->hw;
-
- DPU_REG_WRITE(c, PP_DSC_MODE, 1);
-}
-
-static void dpu_hw_pp_dsc_disable(struct dpu_hw_pingpong *pp)
-{
- struct dpu_hw_blk_reg_map *c;
- u32 data;
-
- if (!pp)
- return;
- c = &pp->hw;
-
- data = DPU_REG_READ(c, PP_DCE_DATA_OUT_SWAP);
- data &= ~BIT(18); /* disable endian flip */
- DPU_REG_WRITE(c, PP_DCE_DATA_OUT_SWAP, data);
-
- DPU_REG_WRITE(c, PP_DSC_MODE, 0);
-}
-
-static int dpu_hw_pp_setup_dsc(struct dpu_hw_pingpong *pp)
-{
- struct dpu_hw_blk_reg_map *c;
- int data;
-
- if (!pp)
- return -EINVAL;
- c = &pp->hw;
-
- data = DPU_REG_READ(c, PP_DCE_DATA_OUT_SWAP);
- data |= BIT(18); /* endian flip */
- DPU_REG_WRITE(c, PP_DCE_DATA_OUT_SWAP, data);
- return 0;
-}
-
static int dpu_hw_pp_setup_dither_v1(struct dpu_hw_pingpong *pp,
void *cfg, size_t len)
{
@@ -339,9 +294,6 @@ static void _setup_pingpong_ops(struct dpu_hw_pingpong_ops *ops,
ops->connect_external_te = dpu_hw_pp_connect_external_te;
ops->get_vsync_info = dpu_hw_pp_get_vsync_info;
ops->setup_autorefresh = dpu_hw_pp_setup_autorefresh_config;
- ops->setup_dsc = dpu_hw_pp_setup_dsc;
- ops->enable_dsc = dpu_hw_pp_dsc_enable;
- ops->disable_dsc = dpu_hw_pp_dsc_disable;
ops->get_autorefresh = dpu_hw_pp_get_autorefresh_config;
ops->poll_timeout_wr_ptr = dpu_hw_pp_poll_timeout_wr_ptr;
ops->get_line_count = dpu_hw_pp_get_line_count;
@@ -48,10 +48,6 @@ struct dpu_hw_pp_vsync_info {
u32 wr_ptr_line_count; /* current line within pp fifo (wr ptr) */
};
-struct dpu_hw_dsc_cfg {
- u8 enable;
-};
-
/**
*
* struct dpu_hw_pingpong_ops : Interface to the pingpong Hw driver functions
@@ -60,9 +56,6 @@ struct dpu_hw_dsc_cfg {
* @enable_tearcheck : enables tear check
* @get_vsync_info : retries timing info of the panel
* @setup_autorefresh : program auto refresh
- * @setup_dsc : program DSC block with encoding details
- * @enable_dsc : enables DSC encoder
- * @disable_dsc : disables DSC encoder
* @setup_dither : function to program the dither hw block
* @get_line_count: obtain current vertical line counter
*/
@@ -113,21 +106,6 @@ struct dpu_hw_pingpong_ops {
int (*poll_timeout_wr_ptr)(struct dpu_hw_pingpong *pp, u32 timeout_us);
/**
- * Program the dsc compression block
- */
- int (*setup_dsc)(struct dpu_hw_pingpong *pp);
-
- /**
- * Enables DSC encoder
- */
- void (*enable_dsc)(struct dpu_hw_pingpong *pp);
-
- /**
- * Disables DSC encoder
- */
- void (*disable_dsc)(struct dpu_hw_pingpong *pp);
-
- /**
* Program the dither hw block
*/
int (*setup_dither)(struct dpu_hw_pingpong *pp, void *cfg, size_t len);
@@ -317,18 +317,6 @@ static void dpu_hw_get_safe_status(struct dpu_hw_mdp *mdp,
status->wb[WB_3] = 0;
}
-static void dpu_hw_setup_dce(struct dpu_hw_mdp *mdp, u32 dce_sel)
-{
- struct dpu_hw_blk_reg_map *c;
-
- if (!mdp)
- return;
-
- c = &mdp->hw;
-
- DPU_REG_WRITE(c, DCE_SEL, dce_sel);
-}
-
void dpu_hw_reset_ubwc(struct dpu_hw_mdp *mdp, struct dpu_mdss_cfg *m)
{
struct dpu_hw_blk_reg_map c;
@@ -367,7 +355,6 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
ops->get_danger_status = dpu_hw_get_danger_status;
ops->setup_vsync_source = dpu_hw_setup_vsync_source;
ops->get_safe_status = dpu_hw_get_safe_status;
- ops->setup_dce = dpu_hw_setup_dce;
ops->reset_ubwc = dpu_hw_reset_ubwc;
ops->intf_audio_select = dpu_hw_intf_audio_select;
}
@@ -143,13 +143,6 @@ struct dpu_hw_mdp_ops {
enum dpu_clk_ctrl_type clk_ctrl, bool enable);
/**
- * setup_dce - set DCE mux for DSC ctrl path
- * @mdp: mdp top context driver
- * @dce_sel: dce_mux value
- */
- void (*setup_dce)(struct dpu_hw_mdp *mdp, u32 dce_sel);
-
- /**
* get_danger_status - get danger status
* @mdp: mdp top context driver
* @status: Pointer to danger safe status
@@ -24,7 +24,6 @@
#include "dpu_hw_wb.h"
#include "dpu_encoder.h"
#include "dpu_connector.h"
-#include "dpu_hw_dsc.h"
#define RESERVED_BY_OTHER(h, r) \
((h)->rsvp && ((h)->rsvp->enc_id != (r)->enc_id))
@@ -49,12 +48,8 @@ struct dpu_rm_topology_def {
static const struct dpu_rm_topology_def g_top_table[] = {
{ DPU_RM_TOPOLOGY_NONE, 0, 0, 0, 0, false },
{ DPU_RM_TOPOLOGY_SINGLEPIPE, 1, 0, 1, 1, false },
- { DPU_RM_TOPOLOGY_SINGLEPIPE_DSC, 1, 1, 1, 1, false },
{ DPU_RM_TOPOLOGY_DUALPIPE, 2, 0, 2, 2, true },
- { DPU_RM_TOPOLOGY_DUALPIPE_DSC, 2, 2, 2, 2, true },
{ DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE, 2, 0, 1, 1, false },
- { DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC, 2, 1, 1, 1, false },
- { DPU_RM_TOPOLOGY_DUALPIPE_DSCMERGE, 2, 2, 1, 1, false },
{ DPU_RM_TOPOLOGY_PPSPLIT, 1, 0, 2, 1, true },
};
@@ -253,9 +248,6 @@ static void _dpu_rm_hw_destroy(enum dpu_hw_blk_type type, void *hw)
case DPU_HW_BLK_WB:
dpu_hw_wb_destroy(hw);
break;
- case DPU_HW_BLK_DSC:
- dpu_hw_dsc_destroy(hw);
- break;
case DPU_HW_BLK_SSPP:
/* SSPPs are not managed by the resource manager */
case DPU_HW_BLK_TOP:
@@ -341,9 +333,6 @@ static int _dpu_rm_hw_blk_create(
case DPU_HW_BLK_WB:
hw = dpu_hw_wb_init(id, mmio, cat, hw_mdp);
break;
- case DPU_HW_BLK_DSC:
- hw = dpu_hw_dsc_init(id, mmio, cat);
- break;
case DPU_HW_BLK_SSPP:
/* SSPPs are not managed by the resource manager */
case DPU_HW_BLK_TOP:
@@ -465,15 +454,6 @@ int dpu_rm_init(struct dpu_rm *rm,
}
}
- for (i = 0; i < cat->dsc_count; i++) {
- rc = _dpu_rm_hw_blk_create(rm, cat, mmio, DPU_HW_BLK_DSC,
- cat->dsc[i].id, &cat->dsc[i]);
- if (rc) {
- DPU_ERROR("failed: dsc hw not available\n");
- goto fail;
- }
- }
-
for (i = 0; i < cat->intf_count; i++) {
if (cat->intf[i].type == INTF_NONE) {
DPU_DEBUG("skip intf %d with type none\n", i);
@@ -834,37 +814,6 @@ static int _dpu_rm_reserve_ctls(
return 0;
}
-static int _dpu_rm_reserve_dsc(
- struct dpu_rm *rm,
- struct dpu_rm_rsvp *rsvp,
- const struct dpu_rm_topology_def *top)
-{
- struct dpu_rm_hw_iter iter;
- int alloc_count = 0;
- int num_dsc_enc = top->num_lm;
-
- if (!top->num_comp_enc)
- return 0;
-
- dpu_rm_init_hw_iter(&iter, 0, DPU_HW_BLK_DSC);
-
- while (_dpu_rm_get_hw_locked(rm, &iter)) {
- if (RESERVED_BY_OTHER(iter.blk, rsvp))
- continue;
-
- iter.blk->rsvp_nxt = rsvp;
- DPU_EVT32(iter.blk->type, rsvp->enc_id, iter.blk->id);
-
- if (++alloc_count == num_dsc_enc)
- return 0;
- }
-
- DPU_ERROR("couldn't reserve %d dsc blocks for enc id %d\n",
- num_dsc_enc, rsvp->enc_id);
-
- return -ENAVAIL;
-}
-
static int _dpu_rm_reserve_cdm(
struct dpu_rm *rm,
struct dpu_rm_rsvp *rsvp,
@@ -1032,10 +981,6 @@ static int _dpu_rm_make_next_rsvp(
if (ret)
return ret;
- ret = _dpu_rm_reserve_dsc(rm, rsvp, reqs->topology);
- if (ret)
- return ret;
-
return ret;
}
@@ -24,23 +24,15 @@
* enum dpu_rm_topology_name - HW resource use case in use by connector
* @DPU_RM_TOPOLOGY_NONE: No topology in use currently
* @DPU_RM_TOPOLOGY_SINGLEPIPE: 1 LM, 1 PP, 1 INTF/WB
- * @DPU_RM_TOPOLOGY_SINGLEPIPE_DSC: 1 LM, 1 DSC, 1 PP, 1 INTF/WB
* @DPU_RM_TOPOLOGY_DUALPIPE: 2 LM, 2 PP, 2 INTF/WB
- * @DPU_RM_TOPOLOGY_DUALPIPE_DSC: 2 LM, 2 DSC, 2 PP, 2 INTF/WB
* @DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE: 2 LM, 2 PP, 3DMux, 1 INTF/WB
- * @DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC: 2 LM, 2 PP, 3DMux, 1 DSC, 1 INTF/WB
- * @DPU_RM_TOPOLOGY_DUALPIPE_DSCMERGE: 2 LM, 2 PP, 2 DSC Merge, 1 INTF/WB
* @DPU_RM_TOPOLOGY_PPSPLIT: 1 LM, 2 PPs, 2 INTF/WB
*/
enum dpu_rm_topology_name {
DPU_RM_TOPOLOGY_NONE = 0,
DPU_RM_TOPOLOGY_SINGLEPIPE,
- DPU_RM_TOPOLOGY_SINGLEPIPE_DSC,
DPU_RM_TOPOLOGY_DUALPIPE,
- DPU_RM_TOPOLOGY_DUALPIPE_DSC,
DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE,
- DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE_DSC,
- DPU_RM_TOPOLOGY_DUALPIPE_DSCMERGE,
DPU_RM_TOPOLOGY_PPSPLIT,
DPU_RM_TOPOLOGY_MAX,
};
@@ -319,20 +319,6 @@ struct msm_display_dsc_info {
};
/**
- * struct msm_compression_info - defined panel compression
- * @comp_type: type of compression supported
- * @dsc_info: dsc configuration if the compression
- * supported is DSC
- */
-struct msm_compression_info {
- enum msm_display_compression_type comp_type;
-
- union{
- struct msm_display_dsc_info dsc_info;
- };
-};
-
-/**
* struct msm_display_topology - defines a display topology pipeline
* @num_lm: number of layer mixers used
* @num_enc: number of compression encoder blocks used
@@ -352,7 +338,6 @@ struct msm_display_topology {
* @jitter_numer: display panel jitter numerator configuration
* @jitter_denom: display panel jitter denominator configuration
* @topology: supported topology for the mode
- * @comp_info: compression info supported
*/
struct msm_mode_info {
uint32_t frame_rate;
@@ -361,7 +346,6 @@ struct msm_mode_info {
uint32_t jitter_numer;
uint32_t jitter_denom;
struct msm_display_topology topology;
- struct msm_compression_info comp_info;
};
/**
Upstream DSI driver doesn't support DSC panels yet. Remove the support for compression from DPU for now. Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> --- drivers/gpu/drm/msm/Makefile | 1 - drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c | 4 - drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.h | 2 +- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 476 +-------------------- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.h | 14 - drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 7 +- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 1 - .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c | 7 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 25 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 16 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c | 252 ----------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h | 100 ----- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_mdss.h | 17 +- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 48 --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 22 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c | 13 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h | 7 - drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c | 55 --- drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h | 8 - drivers/gpu/drm/msm/msm_drv.h | 16 - 20 files changed, 7 insertions(+), 1084 deletions(-) delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.c delete mode 100644 drivers/gpu/drm/msm/disp/dpu1/dpu_hw_dsc.h