diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
index 1237efc..f7e9f76 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c
@@ -41,8 +41,8 @@
 	{DPU_RM_TOPOLOGY_SINGLEPIPE,	"dpu_singlepipe"},
 	{DPU_RM_TOPOLOGY_DUALPIPE,	"dpu_dualpipe"},
 	{DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE,	"dpu_dualpipemerge"},
-	{DPU_RM_TOPOLOGY_PPSPLIT,	"dpu_ppsplit"},
 };
+
 static const struct drm_prop_enum_list e_topology_control[] = {
 	{DPU_RM_TOPCTL_RESERVE_LOCK,	"reserve_lock"},
 	{DPU_RM_TOPCTL_RESERVE_CLEAR,	"reserve_clear"},
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 516458e..8e464fa 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -1914,23 +1914,6 @@ static void _dpu_crtc_setup_mixers(struct drm_crtc *crtc)
 	mutex_unlock(&dpu_crtc->crtc_lock);
 }
 
-static void _dpu_crtc_setup_is_ppsplit(struct drm_crtc_state *state)
-{
-	int i;
-	struct dpu_crtc_state *cstate;
-
-	cstate = to_dpu_crtc_state(state);
-
-	cstate->is_ppsplit = false;
-	for (i = 0; i < cstate->num_connectors; i++) {
-		struct drm_connector *conn = cstate->connectors[i];
-
-		if (dpu_connector_get_topology_name(conn) ==
-				DPU_RM_TOPOLOGY_PPSPLIT)
-			cstate->is_ppsplit = true;
-	}
-}
-
 static void _dpu_crtc_setup_lm_bounds(struct drm_crtc *crtc,
 		struct drm_crtc_state *state)
 {
@@ -1993,7 +1976,6 @@ static void dpu_crtc_atomic_begin(struct drm_crtc *crtc,
 
 	if (!dpu_crtc->num_mixers) {
 		_dpu_crtc_setup_mixers(crtc);
-		_dpu_crtc_setup_is_ppsplit(crtc->state);
 		_dpu_crtc_setup_lm_bounds(crtc, crtc->state);
 	}
 
@@ -2901,7 +2883,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc,
 
 	mixer_width = dpu_crtc_get_mixer_width(dpu_crtc, cstate, mode);
 
-	_dpu_crtc_setup_is_ppsplit(state);
 	_dpu_crtc_setup_lm_bounds(crtc, state);
 
 	 /* get plane state for all drm planes associated with crtc state */
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index 6f12355..32375b1 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -545,7 +545,6 @@ void dpu_encoder_helper_split_config(
 	struct dpu_encoder_virt *dpu_enc;
 	struct split_pipe_cfg cfg = { 0 };
 	struct dpu_hw_mdp *hw_mdptop;
-	enum dpu_rm_topology_name topology;
 	struct msm_display_info *disp_info;
 
 	if (!phys_enc || !phys_enc->hw_mdptop || !phys_enc->parent) {
@@ -569,8 +568,6 @@ void dpu_encoder_helper_split_config(
 	if (phys_enc->split_role == ENC_ROLE_SOLO) {
 		if (hw_mdptop->ops.setup_split_pipe)
 			hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
-		if (hw_mdptop->ops.setup_pp_split)
-			hw_mdptop->ops.setup_pp_split(hw_mdptop, &cfg);
 		return;
 	}
 
@@ -582,29 +579,11 @@ void dpu_encoder_helper_split_config(
 			phys_enc->ops.needs_single_flush(phys_enc))
 		cfg.split_flush_en = true;
 
-	topology = dpu_connector_get_topology_name(phys_enc->connector);
-	if (topology == DPU_RM_TOPOLOGY_PPSPLIT)
-		cfg.pp_split_slave = cfg.intf;
-	else
-		cfg.pp_split_slave = INTF_MAX;
-
 	if (phys_enc->split_role == ENC_ROLE_MASTER) {
 		DPU_DEBUG_ENC(dpu_enc, "enable %d\n", cfg.en);
 
 		if (hw_mdptop->ops.setup_split_pipe)
 			hw_mdptop->ops.setup_split_pipe(hw_mdptop, &cfg);
-	} else if (dpu_enc->hw_pp[0]) {
-		/*
-		 * slave encoder
-		 * - determine split index from master index,
-		 *   assume master is first pp
-		 */
-		cfg.pp_split_index = dpu_enc->hw_pp[0]->idx - PINGPONG_0;
-		DPU_DEBUG_ENC(dpu_enc, "master using pp%d\n",
-				cfg.pp_split_index);
-
-		if (hw_mdptop->ops.setup_pp_split)
-			hw_mdptop->ops.setup_pp_split(hw_mdptop, &cfg);
 	}
 }
 
@@ -1665,14 +1644,6 @@ static inline void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc,
 		return;
 	}
 
-	if (phys->split_role == ENC_ROLE_SKIP) {
-		DPU_DEBUG_ENC(to_dpu_encoder_virt(phys->parent),
-				"skip flush pp%d ctl%d\n",
-				phys->hw_pp->idx - PINGPONG_0,
-				ctl->idx - CTL_0);
-		return;
-	}
-
 	pending_kickoff_cnt = dpu_encoder_phys_inc_pending(phys);
 
 	if (extra_flush_bits && ctl->ops.update_pending_flush)
@@ -1694,8 +1665,6 @@ static inline void _dpu_encoder_trigger_flush(struct drm_encoder *drm_enc,
  */
 static inline void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys)
 {
-	struct dpu_hw_ctl *ctl;
-
 	if (!phys) {
 		DPU_ERROR("invalid argument(s)\n");
 		return;
@@ -1706,14 +1675,6 @@ static inline void _dpu_encoder_trigger_start(struct dpu_encoder_phys *phys)
 		return;
 	}
 
-	ctl = phys->hw_ctl;
-	if (phys->split_role == ENC_ROLE_SKIP) {
-		DPU_DEBUG_ENC(to_dpu_encoder_virt(phys->parent),
-				"skip start pp%d ctl%d\n",
-				phys->hw_pp->idx - PINGPONG_0,
-				ctl->idx - CTL_0);
-		return;
-	}
 	if (phys->ops.trigger_start && phys->enable_state != DPU_ENC_DISABLED)
 		phys->ops.trigger_start(phys);
 }
@@ -1832,7 +1793,6 @@ static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc)
 	/* don't perform flush/start operations for slave encoders */
 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
 		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
-		enum dpu_rm_topology_name topology = DPU_RM_TOPOLOGY_NONE;
 
 		if (!phys || phys->enable_state == DPU_ENC_DISABLED)
 			continue;
@@ -1841,17 +1801,7 @@ static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc)
 		if (!ctl)
 			continue;
 
-		if (phys->connector)
-			topology = dpu_connector_get_topology_name(
-					phys->connector);
-
-		/*
-		 * don't wait on ppsplit slaves or skipped encoders because
-		 * they dont receive irqs
-		 */
-		if (!(topology == DPU_RM_TOPOLOGY_PPSPLIT &&
-				phys->split_role == ENC_ROLE_SLAVE) &&
-				phys->split_role != ENC_ROLE_SKIP)
+		if (phys->split_role != ENC_ROLE_SLAVE)
 			set_bit(i, dpu_enc->frame_busy_mask);
 		if (phys->hw_ctl->ops.reg_dma_flush)
 			phys->hw_ctl->ops.reg_dma_flush(phys->hw_ctl);
@@ -1875,126 +1825,6 @@ static void _dpu_encoder_kickoff_phys(struct dpu_encoder_virt *dpu_enc)
 	spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
 }
 
-static void _dpu_encoder_ppsplit_swap_intf_for_right_only_update(
-		struct drm_encoder *drm_enc,
-		unsigned long *affected_displays,
-		int num_active_phys)
-{
-	struct dpu_encoder_virt *dpu_enc;
-	struct dpu_encoder_phys *master;
-	enum dpu_rm_topology_name topology;
-	bool is_right_only;
-
-	if (!drm_enc || !affected_displays)
-		return;
-
-	dpu_enc = to_dpu_encoder_virt(drm_enc);
-	master = dpu_enc->cur_master;
-	if (!master || !master->connector)
-		return;
-
-	topology = dpu_connector_get_topology_name(master->connector);
-	if (topology != DPU_RM_TOPOLOGY_PPSPLIT)
-		return;
-
-	/*
-	 * For pingpong split, the slave pingpong won't generate IRQs. For
-	 * right-only updates, we can't swap pingpongs, or simply swap the
-	 * master/slave assignment, we actually have to swap the interfaces
-	 * so that the master physical encoder will use a pingpong/interface
-	 * that generates irqs on which to wait.
-	 */
-	is_right_only = !test_bit(0, affected_displays) &&
-			test_bit(1, affected_displays);
-
-	if (is_right_only && !dpu_enc->intfs_swapped) {
-		/* right-only update swap interfaces */
-		swap(dpu_enc->phys_encs[0]->intf_idx,
-				dpu_enc->phys_encs[1]->intf_idx);
-		dpu_enc->intfs_swapped = true;
-	} else if (!is_right_only && dpu_enc->intfs_swapped) {
-		/* left-only or full update, swap back */
-		swap(dpu_enc->phys_encs[0]->intf_idx,
-				dpu_enc->phys_encs[1]->intf_idx);
-		dpu_enc->intfs_swapped = false;
-	}
-
-	DPU_DEBUG_ENC(dpu_enc,
-			"right_only %d swapped %d phys0->intf%d, phys1->intf%d\n",
-			is_right_only, dpu_enc->intfs_swapped,
-			dpu_enc->phys_encs[0]->intf_idx - INTF_0,
-			dpu_enc->phys_encs[1]->intf_idx - INTF_0);
-	DPU_EVT32(DRMID(drm_enc), is_right_only, dpu_enc->intfs_swapped,
-			dpu_enc->phys_encs[0]->intf_idx - INTF_0,
-			dpu_enc->phys_encs[1]->intf_idx - INTF_0,
-			*affected_displays);
-
-	/* ppsplit always uses master since ppslave invalid for irqs*/
-	if (num_active_phys == 1)
-		*affected_displays = BIT(0);
-}
-
-static void _dpu_encoder_update_master(struct drm_encoder *drm_enc,
-		struct dpu_encoder_kickoff_params *params)
-{
-	struct dpu_encoder_virt *dpu_enc;
-	struct dpu_encoder_phys *phys;
-	int i, num_active_phys;
-	bool master_assigned = false;
-
-	if (!drm_enc || !params)
-		return;
-
-	dpu_enc = to_dpu_encoder_virt(drm_enc);
-
-	if (dpu_enc->num_phys_encs <= 1)
-		return;
-
-	/* count bits set */
-	num_active_phys = hweight_long(params->affected_displays);
-
-	DPU_DEBUG_ENC(dpu_enc, "affected_displays 0x%lx num_active_phys %d\n",
-			params->affected_displays, num_active_phys);
-
-	/* for left/right only update, ppsplit master switches interface */
-	_dpu_encoder_ppsplit_swap_intf_for_right_only_update(drm_enc,
-			&params->affected_displays, num_active_phys);
-
-	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
-		enum dpu_enc_split_role prv_role, new_role;
-		bool active;
-
-		phys = dpu_enc->phys_encs[i];
-		if (!phys || !phys->ops.update_split_role || !phys->hw_pp)
-			continue;
-
-		active = test_bit(i, &params->affected_displays);
-		prv_role = phys->split_role;
-
-		if (active && num_active_phys == 1)
-			new_role = ENC_ROLE_SOLO;
-		else if (active && !master_assigned)
-			new_role = ENC_ROLE_MASTER;
-		else if (active)
-			new_role = ENC_ROLE_SLAVE;
-		else
-			new_role = ENC_ROLE_SKIP;
-
-		phys->ops.update_split_role(phys, new_role);
-		if (new_role == ENC_ROLE_SOLO || new_role == ENC_ROLE_MASTER) {
-			dpu_enc->cur_master = phys;
-			master_assigned = true;
-		}
-
-		DPU_DEBUG_ENC(dpu_enc, "pp %d role prv %d new %d active %d\n",
-				phys->hw_pp->idx - PINGPONG_0, prv_role,
-				phys->split_role, active);
-		DPU_EVT32(DRMID(drm_enc), params->affected_displays,
-				phys->hw_pp->idx - PINGPONG_0, prv_role,
-				phys->split_role, active, num_active_phys);
-	}
-}
-
 bool dpu_encoder_check_mode(struct drm_encoder *drm_enc, u32 mode)
 {
 	struct dpu_encoder_virt *dpu_enc;
@@ -2048,15 +1878,10 @@ static void _dpu_encoder_setup_dither(struct dpu_encoder_phys *phys)
 	void *dither_cfg;
 	int ret = 0;
 	size_t len = 0;
-	enum dpu_rm_topology_name topology;
 
 	if (!phys || !phys->connector || !phys->hw_pp ||
 			!phys->hw_pp->ops.setup_dither)
 		return;
-	topology = dpu_connector_get_topology_name(phys->connector);
-	if ((topology == DPU_RM_TOPOLOGY_PPSPLIT) &&
-			(phys->split_role == ENC_ROLE_SLAVE))
-		return;
 
 	ret = dpu_connector_get_dither_cfg(phys->connector,
 				phys->connector->state, &dither_cfg, &len);
@@ -2267,8 +2092,6 @@ void dpu_encoder_prepare_for_kickoff(struct drm_encoder *drm_enc,
 		}
 	}
 
-	_dpu_encoder_update_master(drm_enc, params);
-
 	if (dpu_enc->cur_master && dpu_enc->cur_master->connector) {
 		rc = dpu_connector_pre_kickoff(dpu_enc->cur_master->connector);
 		if (rc)
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
index 4e2e6c6..69ec2b6 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h
@@ -40,13 +40,11 @@
  * @ENC_ROLE_SOLO:	This is the one and only panel. This encoder is master.
  * @ENC_ROLE_MASTER:	This encoder is the master of a split panel config.
  * @ENC_ROLE_SLAVE:	This encoder is not the master of a split panel config.
- * @ENC_ROLE_SKIP:	This encoder is not participating in kickoffs
  */
 enum dpu_enc_split_role {
 	ENC_ROLE_SOLO,
 	ENC_ROLE_MASTER,
 	ENC_ROLE_SLAVE,
-	ENC_ROLE_SKIP
 };
 
 /**
@@ -123,7 +121,6 @@ struct dpu_encoder_virt_ops {
  * @hw_reset:			Issue HW recovery such as CTL reset and clear
  *				DPU_ENC_ERR_NEEDS_HW_RESET state
  * @irq_control:		Handler to enable/disable all the encoder IRQs
- * @update_split_role:		Update the split role of the phys enc
  * @prepare_idle_pc:		phys encoder can update the vsync_enable status
  *                              on idle power collapse prepare
  * @restore:			Restore all the encoder configs.
@@ -167,8 +164,6 @@ struct dpu_encoder_phys_ops {
 	u32 (*collect_misr)(struct dpu_encoder_phys *phys_enc);
 	void (*hw_reset)(struct dpu_encoder_phys *phys_enc);
 	void (*irq_control)(struct dpu_encoder_phys *phys, bool enable);
-	void (*update_split_role)(struct dpu_encoder_phys *phys_enc,
-			enum dpu_enc_split_role role);
 	void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc);
 	void (*restore)(struct dpu_encoder_phys *phys);
 	bool (*is_autorefresh_enabled)(struct dpu_encoder_phys *phys);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
index 71e2e5a..3436788 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c
@@ -114,29 +114,6 @@ static void _dpu_encoder_phys_cmd_config_autorefresh(
 		hw_pp->ops.setup_autorefresh(hw_pp, cfg_cur);
 }
 
-static void _dpu_encoder_phys_cmd_update_flush_mask(
-		struct dpu_encoder_phys *phys_enc)
-{
-	struct dpu_encoder_phys_cmd *cmd_enc =
-			to_dpu_encoder_phys_cmd(phys_enc);
-	struct dpu_hw_ctl *ctl;
-	u32 flush_mask = 0;
-
-	if (!phys_enc)
-		return;
-
-	ctl = phys_enc->hw_ctl;
-	if (!ctl || !ctl->ops.get_bitmask_intf ||
-			!ctl->ops.update_pending_flush)
-		return;
-
-	ctl->ops.get_bitmask_intf(ctl, &flush_mask, phys_enc->intf_idx);
-	ctl->ops.update_pending_flush(ctl, flush_mask);
-
-	DPU_DEBUG_CMDENC(cmd_enc, "update pending flush ctl %d flush_mask %x\n",
-			ctl->idx - CTL_0, flush_mask);
-}
-
 static void _dpu_encoder_phys_cmd_update_intf_cfg(
 		struct dpu_encoder_phys *phys_enc)
 {
@@ -324,20 +301,6 @@ static void dpu_encoder_phys_cmd_mode_set(
 	_dpu_encoder_phys_cmd_setup_irq_hw_idx(phys_enc);
 }
 
-static bool _dpu_encoder_phys_is_ppsplit(struct dpu_encoder_phys *phys_enc)
-{
-	enum dpu_rm_topology_name topology;
-
-	if (!phys_enc)
-		return false;
-
-	topology = dpu_connector_get_topology_name(phys_enc->connector);
-	if (topology == DPU_RM_TOPOLOGY_PPSPLIT)
-		return true;
-
-	return false;
-}
-
 static int _dpu_encoder_phys_cmd_handle_ppdone_timeout(
 		struct dpu_encoder_phys *phys_enc)
 {
@@ -389,16 +352,6 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout(
 	return -ETIMEDOUT;
 }
 
-static bool _dpu_encoder_phys_is_ppsplit_slave(
-		struct dpu_encoder_phys *phys_enc)
-{
-	if (!phys_enc)
-		return false;
-
-	return _dpu_encoder_phys_is_ppsplit(phys_enc) &&
-			phys_enc->split_role == ENC_ROLE_SLAVE;
-}
-
 static int _dpu_encoder_phys_cmd_poll_write_pointer_started(
 		struct dpu_encoder_phys *phys_enc)
 {
@@ -483,10 +436,6 @@ static int _dpu_encoder_phys_cmd_wait_for_idle(
 	wait_info.atomic_cnt = &phys_enc->pending_kickoff_cnt;
 	wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
 
-	/* slave encoder doesn't enable for ppsplit */
-	if (_dpu_encoder_phys_is_ppsplit_slave(phys_enc))
-		return 0;
-
 	ret = dpu_encoder_helper_wait_for_irq(phys_enc, INTR_IDX_PINGPONG,
 			&wait_info);
 	if (ret == -ETIMEDOUT)
@@ -588,7 +537,7 @@ void dpu_encoder_phys_cmd_irq_control(struct dpu_encoder_phys *phys_enc,
 {
 	struct dpu_encoder_phys_cmd *cmd_enc;
 
-	if (!phys_enc || _dpu_encoder_phys_is_ppsplit_slave(phys_enc))
+	if (!phys_enc)
 		return;
 
 	cmd_enc = to_dpu_encoder_phys_cmd(phys_enc);
@@ -726,18 +675,18 @@ static void _dpu_encoder_phys_cmd_pingpong_config(
 			phys_enc->hw_pp->idx - PINGPONG_0);
 	drm_mode_debug_printmodeline(&phys_enc->cached_mode);
 
-	if (!_dpu_encoder_phys_is_ppsplit_slave(phys_enc))
-		_dpu_encoder_phys_cmd_update_intf_cfg(phys_enc);
+	_dpu_encoder_phys_cmd_update_intf_cfg(phys_enc);
 	dpu_encoder_phys_cmd_tearcheck_config(phys_enc);
 }
 
 static bool dpu_encoder_phys_cmd_needs_single_flush(
 		struct dpu_encoder_phys *phys_enc)
 {
-	if (!phys_enc)
-		return false;
-
-	return _dpu_encoder_phys_is_ppsplit(phys_enc);
+	/**
+	 * we do separate flush for each CTL and let
+	 * CTL_START synchronize them
+	 */
+	return false;
 }
 
 static void dpu_encoder_phys_cmd_enable_helper(
@@ -755,12 +704,7 @@ static void dpu_encoder_phys_cmd_enable_helper(
 
 	_dpu_encoder_phys_cmd_pingpong_config(phys_enc);
 
-	/*
-	 * For pp-split, skip setting the flush bit for the slave intf, since
-	 * both intfs use same ctl and HW will only flush the master.
-	 */
-	if (_dpu_encoder_phys_is_ppsplit(phys_enc) &&
-		!dpu_encoder_phys_cmd_is_master(phys_enc))
+	if (!dpu_encoder_phys_cmd_is_master(phys_enc))
 		goto skip_flush;
 
 	ctl = phys_enc->hw_ctl;
@@ -963,10 +907,6 @@ static int _dpu_encoder_phys_cmd_wait_for_ctl_start(
 	wait_info.atomic_cnt = &phys_enc->pending_ctlstart_cnt;
 	wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
 
-	/* slave encoder doesn't enable for ppsplit */
-	if (_dpu_encoder_phys_is_ppsplit_slave(phys_enc))
-		return 0;
-
 	ret = dpu_encoder_helper_wait_for_irq(phys_enc, INTR_IDX_CTL_START,
 			&wait_info);
 	if (ret == -ETIMEDOUT) {
@@ -1053,39 +993,6 @@ static int dpu_encoder_phys_cmd_wait_for_vblank(
 	return rc;
 }
 
-static void dpu_encoder_phys_cmd_update_split_role(
-		struct dpu_encoder_phys *phys_enc,
-		enum dpu_enc_split_role role)
-{
-	struct dpu_encoder_phys_cmd *cmd_enc;
-	enum dpu_enc_split_role old_role;
-	bool is_ppsplit;
-
-	if (!phys_enc)
-		return;
-
-	cmd_enc = to_dpu_encoder_phys_cmd(phys_enc);
-	old_role = phys_enc->split_role;
-	is_ppsplit = _dpu_encoder_phys_is_ppsplit(phys_enc);
-
-	phys_enc->split_role = role;
-
-	DPU_DEBUG_CMDENC(cmd_enc, "old role %d new role %d\n",
-			old_role, role);
-
-	/*
-	 * ppsplit solo needs to reprogram because intf may have swapped without
-	 * role changing on left-only, right-only back-to-back commits
-	 */
-	if (!(is_ppsplit && role == ENC_ROLE_SOLO) &&
-			(role == old_role || role == ENC_ROLE_SKIP))
-		return;
-
-	dpu_encoder_helper_split_config(phys_enc, phys_enc->intf_idx);
-	_dpu_encoder_phys_cmd_pingpong_config(phys_enc);
-	_dpu_encoder_phys_cmd_update_flush_mask(phys_enc);
-}
-
 static void dpu_encoder_phys_cmd_prepare_commit(
 		struct dpu_encoder_phys *phys_enc)
 {
@@ -1191,7 +1098,6 @@ static void dpu_encoder_phys_cmd_init_ops(
 	ops->needs_single_flush = dpu_encoder_phys_cmd_needs_single_flush;
 	ops->hw_reset = dpu_encoder_helper_hw_reset;
 	ops->irq_control = dpu_encoder_phys_cmd_irq_control;
-	ops->update_split_role = dpu_encoder_phys_cmd_update_split_role;
 	ops->restore = dpu_encoder_phys_cmd_enable_helper;
 	ops->prepare_idle_pc = dpu_encoder_phys_cmd_prepare_idle_pc;
 	ops->is_autorefresh_enabled =
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
index d6b72a3..b680718 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_vid.c
@@ -354,20 +354,6 @@ static void dpu_encoder_phys_vid_underrun_irq(void *arg, int irq_idx)
 			phys_enc);
 }
 
-static bool _dpu_encoder_phys_is_ppsplit(struct dpu_encoder_phys *phys_enc)
-{
-	enum dpu_rm_topology_name topology;
-
-	if (!phys_enc)
-		return false;
-
-	topology = dpu_connector_get_topology_name(phys_enc->connector);
-	if (topology == DPU_RM_TOPOLOGY_PPSPLIT)
-		return true;
-
-	return false;
-}
-
 static bool _dpu_encoder_phys_is_dual_ctl(struct dpu_encoder_phys *phys_enc)
 {
 	enum dpu_rm_topology_name topology;
@@ -385,8 +371,7 @@ static bool _dpu_encoder_phys_is_dual_ctl(struct dpu_encoder_phys *phys_enc)
 static bool dpu_encoder_phys_vid_needs_single_flush(
 		struct dpu_encoder_phys *phys_enc)
 {
-	return phys_enc && (_dpu_encoder_phys_is_ppsplit(phys_enc) ||
-		_dpu_encoder_phys_is_dual_ctl(phys_enc));
+	return (phys_enc && _dpu_encoder_phys_is_dual_ctl(phys_enc));
 }
 
 static void _dpu_encoder_phys_vid_setup_irq_hw_idx(
@@ -609,9 +594,7 @@ static int _dpu_encoder_phys_vid_wait_for_vblank(
 	wait_info.timeout_ms = KICKOFF_TIMEOUT_MS;
 
 	if (!dpu_encoder_phys_vid_is_master(phys_enc)) {
-		/* signal done for slave video encoder, unless it is pp-split */
-		if (!_dpu_encoder_phys_is_ppsplit(phys_enc) &&
-			notify && phys_enc->parent_ops.handle_frame_done)
+		if (notify && phys_enc->parent_ops.handle_frame_done)
 			phys_enc->parent_ops.handle_frame_done(
 					phys_enc->parent, phys_enc,
 					DPU_ENCODER_FRAME_EVENT_DONE);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
index 14e66ca..8e779c0 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c
@@ -43,7 +43,7 @@
 #define PINGPONG_SDM845_MASK BIT(DPU_PINGPONG_DITHER)
 
 #define PINGPONG_SDM845_SPLIT_MASK \
-	(PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_SPLIT) | BIT(DPU_PINGPONG_TE2))
+	(PINGPONG_SDM845_MASK | BIT(DPU_PINGPONG_TE2))
 
 #define WB2_SDM845_MASK \
 	(BIT(DPU_WB_LINE_MODE) | BIT(DPU_WB_TRAFFIC_SHAPER) | BIT(DPU_WB_CDP) |\
@@ -119,8 +119,7 @@
 	{
 	.name = "ctl_0", .id = CTL_0,
 	.base = 0x2000, .len = 0xE4,
-	.features = BIT(DPU_CTL_SPLIT_DISPLAY) |
-		BIT(DPU_CTL_PINGPONG_SPLIT)
+	.features = BIT(DPU_CTL_SPLIT_DISPLAY)
 	},
 	{
 	.name = "ctl_1", .id = CTL_1,
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
index ceff3b7..39bec0a 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h
@@ -214,12 +214,10 @@ enum {
 /**
  * CTL sub-blocks
  * @DPU_CTL_SPLIT_DISPLAY       CTL supports video mode split display
- * @DPU_CTL_PINGPONG_SPLIT      CTL supports pingpong split
  * @DPU_CTL_MAX
  */
 enum {
 	DPU_CTL_SPLIT_DISPLAY = 0x1,
-	DPU_CTL_PINGPONG_SPLIT,
 	DPU_CTL_MAX
 };
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
index 60e4bef..8f7f932 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.c
@@ -80,11 +80,6 @@ static void dpu_hw_setup_split_pipe(struct dpu_hw_mdp *mdp,
 				lower_pipe |= FLD_INTF_1_SW_TRG_MUX;
 			else
 				lower_pipe |= FLD_INTF_2_SW_TRG_MUX;
-
-			/* free run */
-			if (cfg->pp_split_slave != INTF_MAX)
-				lower_pipe = FLD_SMART_PANEL_FREE_RUN;
-
 			upper_pipe = lower_pipe;
 		} else {
 			if (cfg->intf == INTF_2) {
@@ -103,33 +98,6 @@ static void dpu_hw_setup_split_pipe(struct dpu_hw_mdp *mdp,
 	DPU_REG_WRITE(c, SPLIT_DISPLAY_EN, cfg->en & 0x1);
 }
 
-static void dpu_hw_setup_pp_split(struct dpu_hw_mdp *mdp,
-		struct split_pipe_cfg *cfg)
-{
-	u32 ppb_config = 0x0;
-	u32 ppb_control = 0x0;
-
-	if (!mdp || !cfg)
-		return;
-
-	if (cfg->en && cfg->pp_split_slave != INTF_MAX) {
-		ppb_config |= (cfg->pp_split_slave - INTF_0 + 1) << 20;
-		ppb_config |= BIT(16); /* split enable */
-		ppb_control = BIT(5); /* horz split*/
-	}
-	if (cfg->pp_split_index) {
-		DPU_REG_WRITE(&mdp->hw, PPB0_CONFIG, 0x0);
-		DPU_REG_WRITE(&mdp->hw, PPB0_CNTL, 0x0);
-		DPU_REG_WRITE(&mdp->hw, PPB1_CONFIG, ppb_config);
-		DPU_REG_WRITE(&mdp->hw, PPB1_CNTL, ppb_control);
-	} else {
-		DPU_REG_WRITE(&mdp->hw, PPB0_CONFIG, ppb_config);
-		DPU_REG_WRITE(&mdp->hw, PPB0_CNTL, ppb_control);
-		DPU_REG_WRITE(&mdp->hw, PPB1_CONFIG, 0x0);
-		DPU_REG_WRITE(&mdp->hw, PPB1_CNTL, 0x0);
-	}
-}
-
 static void dpu_hw_setup_cdm_output(struct dpu_hw_mdp *mdp,
 		struct cdm_output_cfg *cfg)
 {
@@ -349,7 +317,6 @@ static void _setup_mdp_ops(struct dpu_hw_mdp_ops *ops,
 		unsigned long cap)
 {
 	ops->setup_split_pipe = dpu_hw_setup_split_pipe;
-	ops->setup_pp_split = dpu_hw_setup_pp_split;
 	ops->setup_cdm_output = dpu_hw_setup_cdm_output;
 	ops->setup_clk_force_ctrl = dpu_hw_setup_clk_force_ctrl;
 	ops->get_danger_status = dpu_hw_get_danger_status;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
index 1470d0f..5429cd5 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_top.h
@@ -41,8 +41,6 @@ struct traffic_shaper_cfg {
  * @en        : Enable/disable dual pipe confguration
  * @mode      : Panel interface mode
  * @intf      : Interface id for main control path
- * @pp_split_slave: Slave interface for ping pong split, INTF_MAX to disable
- * @pp_split_idx:   Ping pong index for ping pong split
  * @split_flush_en: Allows both the paths to be flushed when master path is
  *              flushed
  */
@@ -50,8 +48,6 @@ struct split_pipe_cfg {
 	bool en;
 	enum dpu_intf_mode mode;
 	enum dpu_intf intf;
-	enum dpu_intf pp_split_slave;
-	u32 pp_split_index;
 	bool split_flush_en;
 };
 
@@ -109,13 +105,6 @@ struct dpu_hw_mdp_ops {
 	void (*setup_split_pipe)(struct dpu_hw_mdp *mdp,
 			struct split_pipe_cfg *p);
 
-	/** setup_pp_split() : Configure pp split related registers
-	 * @mdp  : mdp top context driver
-	 * @cfg  : upper and lower part of pipe configuration
-	 */
-	void (*setup_pp_split)(struct dpu_hw_mdp *mdp,
-			struct split_pipe_cfg *cfg);
-
 	/**
 	 * setup_cdm_output() : Setup selection control of the cdm data path
 	 * @mdp  : mdp top context driver
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h
index b887082..5b2bc9b 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hwio.h
@@ -36,10 +36,6 @@
 #define DSPP_IGC_COLOR0_RAM_LUTN        0x300
 #define DSPP_IGC_COLOR1_RAM_LUTN        0x304
 #define DSPP_IGC_COLOR2_RAM_LUTN        0x308
-#define PPB0_CNTL                       0x330
-#define PPB0_CONFIG                     0x334
-#define PPB1_CNTL                       0x338
-#define PPB1_CONFIG                     0x33C
 #define HW_EVENTS_CTL                   0x37C
 #define CLK_CTRL3                       0x3A8
 #define CLK_STATUS3                     0x3AC
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index 13efbeb..c8c12d3 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -50,7 +50,6 @@ struct dpu_rm_topology_def {
 	{   DPU_RM_TOPOLOGY_SINGLEPIPE,           1, 0, 1, 1, false },
 	{   DPU_RM_TOPOLOGY_DUALPIPE,             2, 0, 2, 2, true  },
 	{   DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE,     2, 0, 1, 1, false },
-	{   DPU_RM_TOPOLOGY_PPSPLIT,              1, 0, 2, 1, true  },
 };
 
 /**
@@ -531,7 +530,6 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
 		struct dpu_rm_hw_blk *primary_lm)
 {
 	const struct dpu_lm_cfg *lm_cfg = to_dpu_hw_mixer(lm->hw)->cap;
-	const struct dpu_pingpong_cfg *pp_cfg;
 	struct dpu_rm_hw_iter iter;
 	bool is_valid_dspp, is_valid_ds, ret;
 
@@ -650,15 +648,6 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
 		return false;
 	}
 
-	pp_cfg = to_dpu_hw_pingpong((*pp)->hw)->caps;
-	if ((reqs->topology->top_name == DPU_RM_TOPOLOGY_PPSPLIT) &&
-			!(test_bit(DPU_PINGPONG_SPLIT, &pp_cfg->features))) {
-		DPU_DEBUG("pp %d doesn't support ppsplit\n", pp_cfg->id);
-		*dspp = NULL;
-		*ds = NULL;
-		return false;
-	}
-
 	return true;
 }
 
@@ -742,26 +731,6 @@ static int _dpu_rm_reserve_lms(
 				ds[i] ? ds[i]->id : 0);
 	}
 
-	if (reqs->topology->top_name == DPU_RM_TOPOLOGY_PPSPLIT) {
-		/* reserve a free PINGPONG_SLAVE block */
-		rc = -ENAVAIL;
-		dpu_rm_init_hw_iter(&iter_i, 0, DPU_HW_BLK_PINGPONG);
-		while (_dpu_rm_get_hw_locked(rm, &iter_i)) {
-			const struct dpu_hw_pingpong *pp =
-					to_dpu_hw_pingpong(iter_i.blk->hw);
-			const struct dpu_pingpong_cfg *pp_cfg = pp->caps;
-
-			if (!(test_bit(DPU_PINGPONG_SLAVE, &pp_cfg->features)))
-				continue;
-			if (RESERVED_BY_OTHER(iter_i.blk, rsvp))
-				continue;
-
-			iter_i.blk->rsvp_nxt = rsvp;
-			rc = 0;
-			break;
-		}
-	}
-
 	return rc;
 }
 
@@ -780,22 +749,18 @@ static int _dpu_rm_reserve_ctls(
 	while (_dpu_rm_get_hw_locked(rm, &iter)) {
 		const struct dpu_hw_ctl *ctl = to_dpu_hw_ctl(iter.blk->hw);
 		unsigned long features = ctl->caps->features;
-		bool has_split_display, has_ppsplit;
+		bool has_split_display;
 
 		if (RESERVED_BY_OTHER(iter.blk, rsvp))
 			continue;
 
 		has_split_display = BIT(DPU_CTL_SPLIT_DISPLAY) & features;
-		has_ppsplit = BIT(DPU_CTL_PINGPONG_SPLIT) & features;
 
 		DPU_DEBUG("ctl %d caps 0x%lX\n", iter.blk->id, features);
 
 		if (top->needs_split_display != has_split_display)
 			continue;
 
-		if (top->top_name == DPU_RM_TOPOLOGY_PPSPLIT && !has_ppsplit)
-			continue;
-
 		ctls[i] = iter.blk;
 		DPU_DEBUG("ctl %d match\n", iter.blk->id);
 
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index 3db61b5..8a6cbcf 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -26,14 +26,12 @@
  * @DPU_RM_TOPOLOGY_SINGLEPIPE:           1 LM, 1 PP, 1 INTF/WB
  * @DPU_RM_TOPOLOGY_DUALPIPE:             2 LM, 2 PP, 2 INTF/WB
  * @DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE:     2 LM, 2 PP, 3DMux, 1 INTF/WB
- * @DPU_RM_TOPOLOGY_PPSPLIT:              1 LM, 2 PPs, 2 INTF/WB
  */
 enum dpu_rm_topology_name {
 	DPU_RM_TOPOLOGY_NONE = 0,
 	DPU_RM_TOPOLOGY_SINGLEPIPE,
 	DPU_RM_TOPOLOGY_DUALPIPE,
 	DPU_RM_TOPOLOGY_DUALPIPE_3DMERGE,
-	DPU_RM_TOPOLOGY_PPSPLIT,
 	DPU_RM_TOPOLOGY_MAX,
 };
 
