| Message ID | 1523902941-2253-4-git-send-email-jsanka@codeaurora.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
On Mon, Apr 16, 2018 at 11:22:18AM -0700, Jeykumar Sankaran wrote: > Remove autorefresh support for smart panels in SDM845 for now. > It needs more discussion to figure out the user space > communication to set preference for the feature. > > Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> Reviewed-by: Sean Paul <seanpaul@chromium.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c | 7 - > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 37 +-- > drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 20 -- > .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 298 +-------------------- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 41 --- > drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 18 -- > 6 files changed, 11 insertions(+), 410 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c > index f7e9f76..dc0978d 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c > @@ -24,9 +24,6 @@ > > #define BL_NODE_NAME_SIZE 32 > > -/* Autorefresh will occur after FRAME_CNT frames. Large values are unlikely */ > -#define AUTOREFRESH_MAX_FRAME_CNT 6 > - > #define DPU_DEBUG_CONN(c, fmt, ...) DPU_DEBUG("conn%d " fmt,\ > (c) ? (c)->base.base.id : -1, ##__VA_ARGS__) > > @@ -1126,10 +1123,6 @@ struct drm_connector *dpu_connector_init(struct drm_device *dev, > CONNECTOR_PROP_AD_BL_SCALE); > #endif > > - msm_property_install_range(&c_conn->property_info, "autorefresh", > - 0x0, 0, AUTOREFRESH_MAX_FRAME_CNT, 0, > - CONNECTOR_PROP_AUTOREFRESH); > - > /* enum/bitmask properties */ > msm_property_install_enum(&c_conn->property_info, "topology_name", > DRM_MODE_PROP_IMMUTABLE, 0, e_topology_name, > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > index 32375b1..3004569 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c > @@ -815,7 +815,6 @@ static void _dpu_encoder_resource_control_helper(struct drm_encoder *drm_enc, > static int dpu_encoder_resource_control(struct drm_encoder *drm_enc, > u32 sw_event) > { > - bool autorefresh_enabled = false; > unsigned int lp, idle_timeout; > struct dpu_encoder_virt *dpu_enc; > struct msm_drm_private *priv; > @@ -922,13 +921,6 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc, > return 0; > } > > - /* schedule delayed off work if autorefresh is disabled */ > - if (dpu_enc->cur_master && > - dpu_enc->cur_master->ops.is_autorefresh_enabled) > - autorefresh_enabled = > - dpu_enc->cur_master->ops.is_autorefresh_enabled( > - dpu_enc->cur_master); > - > /* set idle timeout based on master connector's lp value */ > if (dpu_enc->cur_master) > lp = dpu_connector_get_lp( > @@ -941,13 +933,12 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc, > else > idle_timeout = dpu_enc->idle_timeout; > > - if (!autorefresh_enabled) > - kthread_queue_delayed_work( > - &disp_thread->worker, > - &dpu_enc->delayed_off_work, > - msecs_to_jiffies(idle_timeout)); > + kthread_queue_delayed_work( > + &disp_thread->worker, > + &dpu_enc->delayed_off_work, > + msecs_to_jiffies(idle_timeout)); > + > DPU_EVT32(DRMID(drm_enc), sw_event, dpu_enc->rc_state, > - autorefresh_enabled, > idle_timeout, DPU_EVTLOG_FUNC_CASE2); > DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work scheduled\n", > sw_event); > @@ -1990,7 +1981,6 @@ static void dpu_encoder_vsync_event_handler(struct timer_list *t) > struct drm_encoder *drm_enc = &dpu_enc->base; > struct msm_drm_private *priv; > struct msm_drm_thread *event_thread; > - bool autorefresh_enabled = false; > > if (!drm_enc->dev || !drm_enc->dev->dev_private || > !drm_enc->crtc) { > @@ -2011,22 +2001,7 @@ static void dpu_encoder_vsync_event_handler(struct timer_list *t) > return; > } > > - if (dpu_enc->cur_master && > - dpu_enc->cur_master->ops.is_autorefresh_enabled) > - autorefresh_enabled = > - dpu_enc->cur_master->ops.is_autorefresh_enabled( > - dpu_enc->cur_master); > - > - /* > - * Queue work to update the vsync event timer > - * if autorefresh is enabled. > - */ > - DPU_EVT32_VERBOSE(autorefresh_enabled); > - if (autorefresh_enabled) > - kthread_queue_work(&event_thread->worker, > - &dpu_enc->vsync_event_work); > - else > - del_timer(&dpu_enc->vsync_event_timer); > + del_timer(&dpu_enc->vsync_event_timer); > } > > static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work) > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > index 69ec2b6..d3bfc99 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h > @@ -124,8 +124,6 @@ struct dpu_encoder_virt_ops { > * @prepare_idle_pc: phys encoder can update the vsync_enable status > * on idle power collapse prepare > * @restore: Restore all the encoder configs. > - * @is_autorefresh_enabled: provides the autorefresh current > - * enable/disable state. > * @get_line_count: Obtain current vertical line count > */ > > @@ -166,7 +164,6 @@ struct dpu_encoder_phys_ops { > void (*irq_control)(struct dpu_encoder_phys *phys, bool enable); > void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc); > void (*restore)(struct dpu_encoder_phys *phys); > - bool (*is_autorefresh_enabled)(struct dpu_encoder_phys *phys); > int (*get_line_count)(struct dpu_encoder_phys *phys); > }; > > @@ -176,8 +173,6 @@ struct dpu_encoder_phys_ops { > * @INTR_IDX_PINGPONG: Pingpong done unterrupt for cmd mode panel > * @INTR_IDX_UNDERRUN: Underrun unterrupt for video and cmd mode panel > * @INTR_IDX_RDPTR: Readpointer done unterrupt for cmd mode panel > - * @INTR_IDX_AUTOREFRESH_DONE: Autorefresh done for cmd mode panel meaning > - * autorefresh has triggered a double buffer flip > */ > enum dpu_intr_idx { > INTR_IDX_VSYNC, > @@ -185,7 +180,6 @@ enum dpu_intr_idx { > INTR_IDX_UNDERRUN, > INTR_IDX_CTL_START, > INTR_IDX_RDPTR, > - INTR_IDX_AUTOREFRESH_DONE, > INTR_IDX_MAX, > }; > > @@ -287,18 +281,6 @@ struct dpu_encoder_phys_vid { > }; > > /** > - * struct dpu_encoder_phys_cmd_autorefresh - autorefresh state tracking > - * @cfg: current active autorefresh configuration > - * @kickoff_cnt: atomic count tracking autorefresh done irq kickoffs pending > - * @kickoff_wq: wait queue for waiting on autorefresh done irq > - */ > -struct dpu_encoder_phys_cmd_autorefresh { > - struct dpu_hw_autorefresh cfg; > - atomic_t kickoff_cnt; > - wait_queue_head_t kickoff_wq; > -}; > - > -/** > * struct dpu_encoder_phys_cmd - sub-class of dpu_encoder_phys to handle command > * mode specific operations > * @base: Baseclass physical encoder structure > @@ -307,7 +289,6 @@ struct dpu_encoder_phys_cmd_autorefresh { > * @serialize_wait4pp: serialize wait4pp feature waits for pp_done interrupt > * after ctl_start instead of before next frame kickoff > * @pp_timeout_report_cnt: number of pingpong done irq timeout errors > - * @autorefresh: autorefresh feature state > * @pending_vblank_cnt: Atomic counter tracking pending wait for VBLANK > * @pending_vblank_wq: Wait queue for blocking until VBLANK received > */ > @@ -316,7 +297,6 @@ struct dpu_encoder_phys_cmd { > int stream_sel; > bool serialize_wait4pp; > int pp_timeout_report_cnt; > - struct dpu_encoder_phys_cmd_autorefresh autorefresh; > atomic_t pending_vblank_cnt; > wait_queue_head_t pending_vblank_wq; > }; > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > index 3436788..072939c 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c > @@ -47,9 +47,7 @@ > static inline int _dpu_encoder_phys_cmd_get_idle_timeout( > struct dpu_encoder_phys_cmd *cmd_enc) > { > - return cmd_enc->autorefresh.cfg.frame_count ? > - cmd_enc->autorefresh.cfg.frame_count * > - KICKOFF_TIMEOUT_MS : KICKOFF_TIMEOUT_MS; > + return KICKOFF_TIMEOUT_MS; > } > > static inline bool dpu_encoder_phys_cmd_is_master( > @@ -68,52 +66,6 @@ static bool dpu_encoder_phys_cmd_mode_fixup( > return true; > } > > -static uint64_t _dpu_encoder_phys_cmd_get_autorefresh_property( > - struct dpu_encoder_phys *phys_enc) > -{ > - struct drm_connector *conn = phys_enc->connector; > - > - if (!conn || !conn->state) > - return 0; > - > - return dpu_connector_get_property(conn->state, > - CONNECTOR_PROP_AUTOREFRESH); > -} > - > -static void _dpu_encoder_phys_cmd_config_autorefresh( > - struct dpu_encoder_phys *phys_enc, > - u32 new_frame_count) > -{ > - struct dpu_encoder_phys_cmd *cmd_enc = > - to_dpu_encoder_phys_cmd(phys_enc); > - struct dpu_hw_pingpong *hw_pp = phys_enc->hw_pp; > - struct drm_connector *conn = phys_enc->connector; > - struct dpu_hw_autorefresh *cfg_cur, cfg_nxt; > - > - if (!conn || !conn->state || !hw_pp) > - return; > - > - cfg_cur = &cmd_enc->autorefresh.cfg; > - > - /* autorefresh property value should be validated already */ > - memset(&cfg_nxt, 0, sizeof(cfg_nxt)); > - cfg_nxt.frame_count = new_frame_count; > - cfg_nxt.enable = (cfg_nxt.frame_count != 0); > - > - DPU_DEBUG_CMDENC(cmd_enc, "autorefresh state %d->%d framecount %d\n", > - cfg_cur->enable, cfg_nxt.enable, cfg_nxt.frame_count); > - DPU_EVT32(DRMID(phys_enc->parent), hw_pp->idx, cfg_cur->enable, > - cfg_nxt.enable, cfg_nxt.frame_count); > - > - /* only proceed on state changes */ > - if (cfg_nxt.enable == cfg_cur->enable) > - return; > - > - memcpy(cfg_cur, &cfg_nxt, sizeof(*cfg_cur)); > - if (hw_pp->ops.setup_autorefresh) > - hw_pp->ops.setup_autorefresh(hw_pp, cfg_cur); > -} > - > static void _dpu_encoder_phys_cmd_update_intf_cfg( > struct dpu_encoder_phys *phys_enc) > { > @@ -164,29 +116,6 @@ static void dpu_encoder_phys_cmd_pp_tx_done_irq(void *arg, int irq_idx) > DPU_ATRACE_END("pp_done_irq"); > } > > -static void dpu_encoder_phys_cmd_autorefresh_done_irq(void *arg, int irq_idx) > -{ > - struct dpu_encoder_phys *phys_enc = arg; > - struct dpu_encoder_phys_cmd *cmd_enc = > - to_dpu_encoder_phys_cmd(phys_enc); > - unsigned long lock_flags; > - int new_cnt; > - > - if (!cmd_enc) > - return; > - > - phys_enc = &cmd_enc->base; > - spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); > - new_cnt = atomic_add_unless(&cmd_enc->autorefresh.kickoff_cnt, -1, 0); > - spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); > - > - DPU_EVT32_IRQ(DRMID(phys_enc->parent), > - phys_enc->hw_pp->idx - PINGPONG_0, new_cnt); > - > - /* Signal any waiting atomic commit thread */ > - wake_up_all(&cmd_enc->autorefresh.kickoff_wq); > -} > - > static void dpu_encoder_phys_cmd_pp_rd_ptr_irq(void *arg, int irq_idx) > { > struct dpu_encoder_phys *phys_enc = arg; > @@ -257,10 +186,6 @@ static void _dpu_encoder_phys_cmd_setup_irq_hw_idx( > irq = &phys_enc->irq[INTR_IDX_UNDERRUN]; > irq->hw_idx = phys_enc->intf_idx; > irq->irq_idx = -EINVAL; > - > - irq = &phys_enc->irq[INTR_IDX_AUTOREFRESH_DONE]; > - irq->hw_idx = phys_enc->hw_pp->idx; > - irq->irq_idx = -EINVAL; > } > > static void dpu_encoder_phys_cmd_mode_set( > @@ -352,73 +277,6 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout( > return -ETIMEDOUT; > } > > -static int _dpu_encoder_phys_cmd_poll_write_pointer_started( > - struct dpu_encoder_phys *phys_enc) > -{ > - struct dpu_encoder_phys_cmd *cmd_enc = > - to_dpu_encoder_phys_cmd(phys_enc); > - struct dpu_hw_pingpong *hw_pp = phys_enc->hw_pp; > - struct dpu_hw_pp_vsync_info info; > - u32 timeout_us = DPU_ENC_WR_PTR_START_TIMEOUT_US; > - int ret; > - > - if (!hw_pp || !hw_pp->ops.get_vsync_info || > - !hw_pp->ops.poll_timeout_wr_ptr) > - return 0; > - > - ret = hw_pp->ops.get_vsync_info(hw_pp, &info); > - if (ret) > - return ret; > - > - DPU_DEBUG_CMDENC(cmd_enc, > - "pp:%d rd_ptr %d wr_ptr %d\n", > - phys_enc->hw_pp->idx - PINGPONG_0, > - info.rd_ptr_line_count, > - info.wr_ptr_line_count); > - DPU_EVT32_VERBOSE(DRMID(phys_enc->parent), > - phys_enc->hw_pp->idx - PINGPONG_0, > - info.wr_ptr_line_count); > - > - ret = hw_pp->ops.poll_timeout_wr_ptr(hw_pp, timeout_us); > - if (ret) { > - DPU_EVT32(DRMID(phys_enc->parent), > - phys_enc->hw_pp->idx - PINGPONG_0, > - timeout_us, > - ret); > - DPU_DBG_DUMP("all", "dbg_bus", "vbif_dbg_bus", "panic"); > - } > - > - return ret; > -} > - > -static bool _dpu_encoder_phys_cmd_is_ongoing_pptx( > - struct dpu_encoder_phys *phys_enc) > -{ > - struct dpu_hw_pingpong *hw_pp; > - struct dpu_hw_pp_vsync_info info; > - > - if (!phys_enc) > - return false; > - > - hw_pp = phys_enc->hw_pp; > - if (!hw_pp || !hw_pp->ops.get_vsync_info) > - return false; > - > - hw_pp->ops.get_vsync_info(hw_pp, &info); > - > - DPU_EVT32(DRMID(phys_enc->parent), > - phys_enc->hw_pp->idx - PINGPONG_0, > - atomic_read(&phys_enc->pending_kickoff_cnt), > - info.wr_ptr_line_count, > - phys_enc->cached_mode.vdisplay); > - > - if (info.wr_ptr_line_count > 0 && info.wr_ptr_line_count < > - phys_enc->cached_mode.vdisplay) > - return true; > - > - return false; > -} > - > static int _dpu_encoder_phys_cmd_wait_for_idle( > struct dpu_encoder_phys *phys_enc) > { > @@ -446,42 +304,6 @@ static int _dpu_encoder_phys_cmd_wait_for_idle( > return ret; > } > > -static int _dpu_encoder_phys_cmd_wait_for_autorefresh_done( > - struct dpu_encoder_phys *phys_enc) > -{ > - struct dpu_encoder_phys_cmd *cmd_enc = > - to_dpu_encoder_phys_cmd(phys_enc); > - struct dpu_encoder_wait_info wait_info; > - int ret = 0; > - > - if (!phys_enc) { > - DPU_ERROR("invalid encoder\n"); > - return -EINVAL; > - } > - > - /* only master deals with autorefresh */ > - if (!dpu_encoder_phys_cmd_is_master(phys_enc)) > - return 0; > - > - wait_info.wq = &cmd_enc->autorefresh.kickoff_wq; > - wait_info.atomic_cnt = &cmd_enc->autorefresh.kickoff_cnt; > - wait_info.timeout_ms = _dpu_encoder_phys_cmd_get_idle_timeout(cmd_enc); > - > - /* wait for autorefresh kickoff to start */ > - ret = dpu_encoder_helper_wait_for_irq(phys_enc, > - INTR_IDX_AUTOREFRESH_DONE, &wait_info); > - > - /* double check that kickoff has started by reading write ptr reg */ > - if (!ret) > - ret = _dpu_encoder_phys_cmd_poll_write_pointer_started( > - phys_enc); > - else > - dpu_encoder_helper_report_irq_timeout(phys_enc, > - INTR_IDX_AUTOREFRESH_DONE); > - > - return ret; > -} > - > static int dpu_encoder_phys_cmd_control_vblank_irq( > struct dpu_encoder_phys *phys_enc, > bool enable) > @@ -550,20 +372,13 @@ void dpu_encoder_phys_cmd_irq_control(struct dpu_encoder_phys *phys_enc, > dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_UNDERRUN); > dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, true); > > - if (dpu_encoder_phys_cmd_is_master(phys_enc)) { > + if (dpu_encoder_phys_cmd_is_master(phys_enc)) > dpu_encoder_helper_register_irq(phys_enc, > INTR_IDX_CTL_START); > - dpu_encoder_helper_register_irq(phys_enc, > - INTR_IDX_AUTOREFRESH_DONE); > - } > - > } else { > - if (dpu_encoder_phys_cmd_is_master(phys_enc)) { > + if (dpu_encoder_phys_cmd_is_master(phys_enc)) > dpu_encoder_helper_unregister_irq(phys_enc, > INTR_IDX_CTL_START); > - dpu_encoder_helper_unregister_irq(phys_enc, > - INTR_IDX_AUTOREFRESH_DONE); > - } > > dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_UNDERRUN); > dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, false); > @@ -736,30 +551,6 @@ static void dpu_encoder_phys_cmd_enable(struct dpu_encoder_phys *phys_enc) > phys_enc->enable_state = DPU_ENC_ENABLED; > } > > -static bool dpu_encoder_phys_cmd_is_autorefresh_enabled( > - struct dpu_encoder_phys *phys_enc) > -{ > - struct dpu_hw_pingpong *hw_pp; > - struct dpu_hw_autorefresh cfg; > - int ret; > - > - if (!phys_enc || !phys_enc->hw_pp) > - return 0; > - > - if (!dpu_encoder_phys_cmd_is_master(phys_enc)) > - return 0; > - > - hw_pp = phys_enc->hw_pp; > - if (!hw_pp->ops.get_autorefresh) > - return 0; > - > - ret = hw_pp->ops.get_autorefresh(hw_pp, &cfg); > - if (ret) > - return 0; > - > - return cfg.enable; > -} > - > static void _dpu_encoder_phys_cmd_connect_te( > struct dpu_encoder_phys *phys_enc, bool enable) > { > @@ -869,8 +660,7 @@ static void dpu_encoder_phys_cmd_prepare_for_kickoff( > DPU_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0); > > DPU_EVT32(DRMID(phys_enc->parent), phys_enc->hw_pp->idx - PINGPONG_0, > - atomic_read(&phys_enc->pending_kickoff_cnt), > - atomic_read(&cmd_enc->autorefresh.kickoff_cnt)); > + atomic_read(&phys_enc->pending_kickoff_cnt)); > > /* > * Mark kickoff request as outstanding. If there are more than one, > @@ -954,10 +744,6 @@ static int dpu_encoder_phys_cmd_wait_for_commit_done( > if (dpu_encoder_phys_cmd_is_master(phys_enc)) > rc = _dpu_encoder_phys_cmd_wait_for_ctl_start(phys_enc); > > - if (!rc && dpu_encoder_phys_cmd_is_master(phys_enc) && > - cmd_enc->autorefresh.cfg.enable) > - rc = _dpu_encoder_phys_cmd_wait_for_autorefresh_done(phys_enc); > - > /* required for both controllers */ > if (!rc && cmd_enc->serialize_wait4pp) > dpu_encoder_phys_cmd_prepare_for_kickoff(phys_enc, NULL); > @@ -993,58 +779,6 @@ static int dpu_encoder_phys_cmd_wait_for_vblank( > return rc; > } > > -static void dpu_encoder_phys_cmd_prepare_commit( > - struct dpu_encoder_phys *phys_enc) > -{ > - struct dpu_encoder_phys_cmd *cmd_enc = > - to_dpu_encoder_phys_cmd(phys_enc); > - unsigned long lock_flags; > - > - if (!phys_enc) > - return; > - > - if (!dpu_encoder_phys_cmd_is_master(phys_enc)) > - return; > - > - DPU_EVT32(DRMID(phys_enc->parent), phys_enc->intf_idx - INTF_0, > - cmd_enc->autorefresh.cfg.enable); > - > - if (!dpu_encoder_phys_cmd_is_autorefresh_enabled(phys_enc)) > - return; > - > - /** > - * Autorefresh must be disabled carefully: > - * - Autorefresh must be disabled between pp_done and te > - * signal prior to sdm845 targets. All targets after sdm845 > - * supports autorefresh disable without turning off the > - * hardware TE and pp_done wait. > - * > - * - Wait for TX to Complete > - * Wait for PPDone confirms the last frame transfer is complete. > - * > - * - Leave Autorefresh Disabled > - * - Assume disable of Autorefresh since it is now safe > - * - Can now safely Disable Encoder, do debug printing, etc. > - * without worrying that Autorefresh will kickoff > - */ > - > - spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); > - > - _dpu_encoder_phys_cmd_config_autorefresh(phys_enc, 0); > - > - /* check for outstanding TX */ > - if (_dpu_encoder_phys_cmd_is_ongoing_pptx(phys_enc)) > - atomic_add_unless(&phys_enc->pending_kickoff_cnt, 1, 1); > - spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); > - > - /* wait for ppdone if necessary due to catching ongoing TX */ > - if (_dpu_encoder_phys_cmd_wait_for_idle(phys_enc)) > - DPU_ERROR_CMDENC(cmd_enc, "pp:%d kickoff timed out\n", > - phys_enc->hw_pp->idx - PINGPONG_0); > - > - DPU_DEBUG_CMDENC(cmd_enc, "disabled autorefresh\n"); > -} > - > static void dpu_encoder_phys_cmd_handle_post_kickoff( > struct dpu_encoder_phys *phys_enc) > { > @@ -1061,27 +795,15 @@ static void dpu_encoder_phys_cmd_handle_post_kickoff( > static void dpu_encoder_phys_cmd_trigger_start( > struct dpu_encoder_phys *phys_enc) > { > - struct dpu_encoder_phys_cmd *cmd_enc = > - to_dpu_encoder_phys_cmd(phys_enc); > - u32 frame_cnt; > - > if (!phys_enc) > return; > > - /* we don't issue CTL_START when using autorefresh */ > - frame_cnt = _dpu_encoder_phys_cmd_get_autorefresh_property(phys_enc); > - if (frame_cnt) { > - _dpu_encoder_phys_cmd_config_autorefresh(phys_enc, frame_cnt); > - atomic_inc(&cmd_enc->autorefresh.kickoff_cnt); > - } else { > - dpu_encoder_helper_trigger_start(phys_enc); > - } > + dpu_encoder_helper_trigger_start(phys_enc); > } > > static void dpu_encoder_phys_cmd_init_ops( > struct dpu_encoder_phys_ops *ops) > { > - ops->prepare_commit = dpu_encoder_phys_cmd_prepare_commit; > ops->is_master = dpu_encoder_phys_cmd_is_master; > ops->mode_set = dpu_encoder_phys_cmd_mode_set; > ops->mode_fixup = dpu_encoder_phys_cmd_mode_fixup; > @@ -1100,8 +822,6 @@ static void dpu_encoder_phys_cmd_init_ops( > ops->irq_control = dpu_encoder_phys_cmd_irq_control; > ops->restore = dpu_encoder_phys_cmd_enable_helper; > ops->prepare_idle_pc = dpu_encoder_phys_cmd_prepare_idle_pc; > - ops->is_autorefresh_enabled = > - dpu_encoder_phys_cmd_is_autorefresh_enabled; > ops->handle_post_kickoff = dpu_encoder_phys_cmd_handle_post_kickoff; > ops->get_line_count = dpu_encoder_phys_cmd_get_line_count; > } > @@ -1175,20 +895,12 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init( > irq->intr_idx = INTR_IDX_UNDERRUN; > irq->cb.func = dpu_encoder_phys_cmd_underrun_irq; > > - irq = &phys_enc->irq[INTR_IDX_AUTOREFRESH_DONE]; > - irq->name = "autorefresh_done"; > - irq->intr_type = DPU_IRQ_TYPE_PING_PONG_AUTO_REF; > - irq->intr_idx = INTR_IDX_AUTOREFRESH_DONE; > - irq->cb.func = dpu_encoder_phys_cmd_autorefresh_done_irq; > - > atomic_set(&phys_enc->vblank_refcount, 0); > atomic_set(&phys_enc->pending_kickoff_cnt, 0); > atomic_set(&phys_enc->pending_ctlstart_cnt, 0); > atomic_set(&cmd_enc->pending_vblank_cnt, 0); > init_waitqueue_head(&phys_enc->pending_kickoff_wq); > init_waitqueue_head(&cmd_enc->pending_vblank_wq); > - atomic_set(&cmd_enc->autorefresh.kickoff_cnt, 0); > - init_waitqueue_head(&cmd_enc->autorefresh.kickoff_wq); > > DPU_DEBUG_CMDENC(cmd_enc, "created\n"); > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c > index 9308f5c..0bfb511 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c > @@ -31,7 +31,6 @@ > #define PP_WR_PTR_IRQ 0x024 > #define PP_OUT_LINE_COUNT 0x028 > #define PP_LINE_COUNT 0x02C > -#define PP_AUTOREFRESH_CONFIG 0x030 > > #define PP_FBC_MODE 0x034 > #define PP_FBC_BUDGET_CTL 0x038 > @@ -93,44 +92,6 @@ static int dpu_hw_pp_setup_te_config(struct dpu_hw_pingpong *pp, > return 0; > } > > -static int dpu_hw_pp_setup_autorefresh_config(struct dpu_hw_pingpong *pp, > - struct dpu_hw_autorefresh *cfg) > -{ > - struct dpu_hw_blk_reg_map *c; > - u32 refresh_cfg; > - > - if (!pp || !cfg) > - return -EINVAL; > - c = &pp->hw; > - > - if (cfg->enable) > - refresh_cfg = BIT(31) | cfg->frame_count; > - else > - refresh_cfg = 0; > - > - DPU_REG_WRITE(c, PP_AUTOREFRESH_CONFIG, refresh_cfg); > - DPU_EVT32(pp->idx - PINGPONG_0, refresh_cfg); > - > - return 0; > -} > - > -static int dpu_hw_pp_get_autorefresh_config(struct dpu_hw_pingpong *pp, > - struct dpu_hw_autorefresh *cfg) > -{ > - struct dpu_hw_blk_reg_map *c; > - u32 val; > - > - if (!pp || !cfg) > - return -EINVAL; > - > - c = &pp->hw; > - val = DPU_REG_READ(c, PP_AUTOREFRESH_CONFIG); > - cfg->enable = (val & BIT(31)) >> 31; > - cfg->frame_count = val & 0xffff; > - > - return 0; > -} > - > static int dpu_hw_pp_poll_timeout_wr_ptr(struct dpu_hw_pingpong *pp, > u32 timeout_us) > { > @@ -293,8 +254,6 @@ static void _setup_pingpong_ops(struct dpu_hw_pingpong_ops *ops, > ops->enable_tearcheck = dpu_hw_pp_enable_te; > ops->connect_external_te = dpu_hw_pp_connect_external_te; > ops->get_vsync_info = dpu_hw_pp_get_vsync_info; > - ops->setup_autorefresh = dpu_hw_pp_setup_autorefresh_config; > - ops->get_autorefresh = dpu_hw_pp_get_autorefresh_config; > ops->poll_timeout_wr_ptr = dpu_hw_pp_poll_timeout_wr_ptr; > ops->get_line_count = dpu_hw_pp_get_line_count; > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h > index 93d03cce..7dbfcae 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h > @@ -36,11 +36,6 @@ struct dpu_hw_tear_check { > u8 hw_vsync_mode; > }; > > -struct dpu_hw_autorefresh { > - bool enable; > - u32 frame_count; > -}; > - > struct dpu_hw_pp_vsync_info { > u32 rd_ptr_init_val; /* value of rd pointer at vsync edge */ > u32 rd_ptr_frame_count; /* num frames sent since enabling interface */ > @@ -55,7 +50,6 @@ struct dpu_hw_pp_vsync_info { > * @setup_tearcheck : program tear check values > * @enable_tearcheck : enables tear check > * @get_vsync_info : retries timing info of the panel > - * @setup_autorefresh : program auto refresh > * @setup_dither : function to program the dither hw block > * @get_line_count: obtain current vertical line counter > */ > @@ -88,18 +82,6 @@ struct dpu_hw_pingpong_ops { > struct dpu_hw_pp_vsync_info *info); > > /** > - * configure and enable the autorefresh config > - */ > - int (*setup_autorefresh)(struct dpu_hw_pingpong *pp, > - struct dpu_hw_autorefresh *cfg); > - > - /** > - * retrieve autorefresh config from hardware > - */ > - int (*get_autorefresh)(struct dpu_hw_pingpong *pp, > - struct dpu_hw_autorefresh *cfg); > - > - /** > * poll until write pointer transmission starts > * @Return: 0 on success, -ETIMEDOUT on timeout > */ > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project >
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c index f7e9f76..dc0978d 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c @@ -24,9 +24,6 @@ #define BL_NODE_NAME_SIZE 32 -/* Autorefresh will occur after FRAME_CNT frames. Large values are unlikely */ -#define AUTOREFRESH_MAX_FRAME_CNT 6 - #define DPU_DEBUG_CONN(c, fmt, ...) DPU_DEBUG("conn%d " fmt,\ (c) ? (c)->base.base.id : -1, ##__VA_ARGS__) @@ -1126,10 +1123,6 @@ struct drm_connector *dpu_connector_init(struct drm_device *dev, CONNECTOR_PROP_AD_BL_SCALE); #endif - msm_property_install_range(&c_conn->property_info, "autorefresh", - 0x0, 0, AUTOREFRESH_MAX_FRAME_CNT, 0, - CONNECTOR_PROP_AUTOREFRESH); - /* enum/bitmask properties */ msm_property_install_enum(&c_conn->property_info, "topology_name", DRM_MODE_PROP_IMMUTABLE, 0, e_topology_name, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c index 32375b1..3004569 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c @@ -815,7 +815,6 @@ static void _dpu_encoder_resource_control_helper(struct drm_encoder *drm_enc, static int dpu_encoder_resource_control(struct drm_encoder *drm_enc, u32 sw_event) { - bool autorefresh_enabled = false; unsigned int lp, idle_timeout; struct dpu_encoder_virt *dpu_enc; struct msm_drm_private *priv; @@ -922,13 +921,6 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc, return 0; } - /* schedule delayed off work if autorefresh is disabled */ - if (dpu_enc->cur_master && - dpu_enc->cur_master->ops.is_autorefresh_enabled) - autorefresh_enabled = - dpu_enc->cur_master->ops.is_autorefresh_enabled( - dpu_enc->cur_master); - /* set idle timeout based on master connector's lp value */ if (dpu_enc->cur_master) lp = dpu_connector_get_lp( @@ -941,13 +933,12 @@ static int dpu_encoder_resource_control(struct drm_encoder *drm_enc, else idle_timeout = dpu_enc->idle_timeout; - if (!autorefresh_enabled) - kthread_queue_delayed_work( - &disp_thread->worker, - &dpu_enc->delayed_off_work, - msecs_to_jiffies(idle_timeout)); + kthread_queue_delayed_work( + &disp_thread->worker, + &dpu_enc->delayed_off_work, + msecs_to_jiffies(idle_timeout)); + DPU_EVT32(DRMID(drm_enc), sw_event, dpu_enc->rc_state, - autorefresh_enabled, idle_timeout, DPU_EVTLOG_FUNC_CASE2); DPU_DEBUG_ENC(dpu_enc, "sw_event:%d, work scheduled\n", sw_event); @@ -1990,7 +1981,6 @@ static void dpu_encoder_vsync_event_handler(struct timer_list *t) struct drm_encoder *drm_enc = &dpu_enc->base; struct msm_drm_private *priv; struct msm_drm_thread *event_thread; - bool autorefresh_enabled = false; if (!drm_enc->dev || !drm_enc->dev->dev_private || !drm_enc->crtc) { @@ -2011,22 +2001,7 @@ static void dpu_encoder_vsync_event_handler(struct timer_list *t) return; } - if (dpu_enc->cur_master && - dpu_enc->cur_master->ops.is_autorefresh_enabled) - autorefresh_enabled = - dpu_enc->cur_master->ops.is_autorefresh_enabled( - dpu_enc->cur_master); - - /* - * Queue work to update the vsync event timer - * if autorefresh is enabled. - */ - DPU_EVT32_VERBOSE(autorefresh_enabled); - if (autorefresh_enabled) - kthread_queue_work(&event_thread->worker, - &dpu_enc->vsync_event_work); - else - del_timer(&dpu_enc->vsync_event_timer); + del_timer(&dpu_enc->vsync_event_timer); } static void dpu_encoder_vsync_event_work_handler(struct kthread_work *work) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h index 69ec2b6..d3bfc99 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h @@ -124,8 +124,6 @@ struct dpu_encoder_virt_ops { * @prepare_idle_pc: phys encoder can update the vsync_enable status * on idle power collapse prepare * @restore: Restore all the encoder configs. - * @is_autorefresh_enabled: provides the autorefresh current - * enable/disable state. * @get_line_count: Obtain current vertical line count */ @@ -166,7 +164,6 @@ struct dpu_encoder_phys_ops { void (*irq_control)(struct dpu_encoder_phys *phys, bool enable); void (*prepare_idle_pc)(struct dpu_encoder_phys *phys_enc); void (*restore)(struct dpu_encoder_phys *phys); - bool (*is_autorefresh_enabled)(struct dpu_encoder_phys *phys); int (*get_line_count)(struct dpu_encoder_phys *phys); }; @@ -176,8 +173,6 @@ struct dpu_encoder_phys_ops { * @INTR_IDX_PINGPONG: Pingpong done unterrupt for cmd mode panel * @INTR_IDX_UNDERRUN: Underrun unterrupt for video and cmd mode panel * @INTR_IDX_RDPTR: Readpointer done unterrupt for cmd mode panel - * @INTR_IDX_AUTOREFRESH_DONE: Autorefresh done for cmd mode panel meaning - * autorefresh has triggered a double buffer flip */ enum dpu_intr_idx { INTR_IDX_VSYNC, @@ -185,7 +180,6 @@ enum dpu_intr_idx { INTR_IDX_UNDERRUN, INTR_IDX_CTL_START, INTR_IDX_RDPTR, - INTR_IDX_AUTOREFRESH_DONE, INTR_IDX_MAX, }; @@ -287,18 +281,6 @@ struct dpu_encoder_phys_vid { }; /** - * struct dpu_encoder_phys_cmd_autorefresh - autorefresh state tracking - * @cfg: current active autorefresh configuration - * @kickoff_cnt: atomic count tracking autorefresh done irq kickoffs pending - * @kickoff_wq: wait queue for waiting on autorefresh done irq - */ -struct dpu_encoder_phys_cmd_autorefresh { - struct dpu_hw_autorefresh cfg; - atomic_t kickoff_cnt; - wait_queue_head_t kickoff_wq; -}; - -/** * struct dpu_encoder_phys_cmd - sub-class of dpu_encoder_phys to handle command * mode specific operations * @base: Baseclass physical encoder structure @@ -307,7 +289,6 @@ struct dpu_encoder_phys_cmd_autorefresh { * @serialize_wait4pp: serialize wait4pp feature waits for pp_done interrupt * after ctl_start instead of before next frame kickoff * @pp_timeout_report_cnt: number of pingpong done irq timeout errors - * @autorefresh: autorefresh feature state * @pending_vblank_cnt: Atomic counter tracking pending wait for VBLANK * @pending_vblank_wq: Wait queue for blocking until VBLANK received */ @@ -316,7 +297,6 @@ struct dpu_encoder_phys_cmd { int stream_sel; bool serialize_wait4pp; int pp_timeout_report_cnt; - struct dpu_encoder_phys_cmd_autorefresh autorefresh; atomic_t pending_vblank_cnt; wait_queue_head_t pending_vblank_wq; }; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c index 3436788..072939c 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c @@ -47,9 +47,7 @@ static inline int _dpu_encoder_phys_cmd_get_idle_timeout( struct dpu_encoder_phys_cmd *cmd_enc) { - return cmd_enc->autorefresh.cfg.frame_count ? - cmd_enc->autorefresh.cfg.frame_count * - KICKOFF_TIMEOUT_MS : KICKOFF_TIMEOUT_MS; + return KICKOFF_TIMEOUT_MS; } static inline bool dpu_encoder_phys_cmd_is_master( @@ -68,52 +66,6 @@ static bool dpu_encoder_phys_cmd_mode_fixup( return true; } -static uint64_t _dpu_encoder_phys_cmd_get_autorefresh_property( - struct dpu_encoder_phys *phys_enc) -{ - struct drm_connector *conn = phys_enc->connector; - - if (!conn || !conn->state) - return 0; - - return dpu_connector_get_property(conn->state, - CONNECTOR_PROP_AUTOREFRESH); -} - -static void _dpu_encoder_phys_cmd_config_autorefresh( - struct dpu_encoder_phys *phys_enc, - u32 new_frame_count) -{ - struct dpu_encoder_phys_cmd *cmd_enc = - to_dpu_encoder_phys_cmd(phys_enc); - struct dpu_hw_pingpong *hw_pp = phys_enc->hw_pp; - struct drm_connector *conn = phys_enc->connector; - struct dpu_hw_autorefresh *cfg_cur, cfg_nxt; - - if (!conn || !conn->state || !hw_pp) - return; - - cfg_cur = &cmd_enc->autorefresh.cfg; - - /* autorefresh property value should be validated already */ - memset(&cfg_nxt, 0, sizeof(cfg_nxt)); - cfg_nxt.frame_count = new_frame_count; - cfg_nxt.enable = (cfg_nxt.frame_count != 0); - - DPU_DEBUG_CMDENC(cmd_enc, "autorefresh state %d->%d framecount %d\n", - cfg_cur->enable, cfg_nxt.enable, cfg_nxt.frame_count); - DPU_EVT32(DRMID(phys_enc->parent), hw_pp->idx, cfg_cur->enable, - cfg_nxt.enable, cfg_nxt.frame_count); - - /* only proceed on state changes */ - if (cfg_nxt.enable == cfg_cur->enable) - return; - - memcpy(cfg_cur, &cfg_nxt, sizeof(*cfg_cur)); - if (hw_pp->ops.setup_autorefresh) - hw_pp->ops.setup_autorefresh(hw_pp, cfg_cur); -} - static void _dpu_encoder_phys_cmd_update_intf_cfg( struct dpu_encoder_phys *phys_enc) { @@ -164,29 +116,6 @@ static void dpu_encoder_phys_cmd_pp_tx_done_irq(void *arg, int irq_idx) DPU_ATRACE_END("pp_done_irq"); } -static void dpu_encoder_phys_cmd_autorefresh_done_irq(void *arg, int irq_idx) -{ - struct dpu_encoder_phys *phys_enc = arg; - struct dpu_encoder_phys_cmd *cmd_enc = - to_dpu_encoder_phys_cmd(phys_enc); - unsigned long lock_flags; - int new_cnt; - - if (!cmd_enc) - return; - - phys_enc = &cmd_enc->base; - spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); - new_cnt = atomic_add_unless(&cmd_enc->autorefresh.kickoff_cnt, -1, 0); - spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); - - DPU_EVT32_IRQ(DRMID(phys_enc->parent), - phys_enc->hw_pp->idx - PINGPONG_0, new_cnt); - - /* Signal any waiting atomic commit thread */ - wake_up_all(&cmd_enc->autorefresh.kickoff_wq); -} - static void dpu_encoder_phys_cmd_pp_rd_ptr_irq(void *arg, int irq_idx) { struct dpu_encoder_phys *phys_enc = arg; @@ -257,10 +186,6 @@ static void _dpu_encoder_phys_cmd_setup_irq_hw_idx( irq = &phys_enc->irq[INTR_IDX_UNDERRUN]; irq->hw_idx = phys_enc->intf_idx; irq->irq_idx = -EINVAL; - - irq = &phys_enc->irq[INTR_IDX_AUTOREFRESH_DONE]; - irq->hw_idx = phys_enc->hw_pp->idx; - irq->irq_idx = -EINVAL; } static void dpu_encoder_phys_cmd_mode_set( @@ -352,73 +277,6 @@ static int _dpu_encoder_phys_cmd_handle_ppdone_timeout( return -ETIMEDOUT; } -static int _dpu_encoder_phys_cmd_poll_write_pointer_started( - struct dpu_encoder_phys *phys_enc) -{ - struct dpu_encoder_phys_cmd *cmd_enc = - to_dpu_encoder_phys_cmd(phys_enc); - struct dpu_hw_pingpong *hw_pp = phys_enc->hw_pp; - struct dpu_hw_pp_vsync_info info; - u32 timeout_us = DPU_ENC_WR_PTR_START_TIMEOUT_US; - int ret; - - if (!hw_pp || !hw_pp->ops.get_vsync_info || - !hw_pp->ops.poll_timeout_wr_ptr) - return 0; - - ret = hw_pp->ops.get_vsync_info(hw_pp, &info); - if (ret) - return ret; - - DPU_DEBUG_CMDENC(cmd_enc, - "pp:%d rd_ptr %d wr_ptr %d\n", - phys_enc->hw_pp->idx - PINGPONG_0, - info.rd_ptr_line_count, - info.wr_ptr_line_count); - DPU_EVT32_VERBOSE(DRMID(phys_enc->parent), - phys_enc->hw_pp->idx - PINGPONG_0, - info.wr_ptr_line_count); - - ret = hw_pp->ops.poll_timeout_wr_ptr(hw_pp, timeout_us); - if (ret) { - DPU_EVT32(DRMID(phys_enc->parent), - phys_enc->hw_pp->idx - PINGPONG_0, - timeout_us, - ret); - DPU_DBG_DUMP("all", "dbg_bus", "vbif_dbg_bus", "panic"); - } - - return ret; -} - -static bool _dpu_encoder_phys_cmd_is_ongoing_pptx( - struct dpu_encoder_phys *phys_enc) -{ - struct dpu_hw_pingpong *hw_pp; - struct dpu_hw_pp_vsync_info info; - - if (!phys_enc) - return false; - - hw_pp = phys_enc->hw_pp; - if (!hw_pp || !hw_pp->ops.get_vsync_info) - return false; - - hw_pp->ops.get_vsync_info(hw_pp, &info); - - DPU_EVT32(DRMID(phys_enc->parent), - phys_enc->hw_pp->idx - PINGPONG_0, - atomic_read(&phys_enc->pending_kickoff_cnt), - info.wr_ptr_line_count, - phys_enc->cached_mode.vdisplay); - - if (info.wr_ptr_line_count > 0 && info.wr_ptr_line_count < - phys_enc->cached_mode.vdisplay) - return true; - - return false; -} - static int _dpu_encoder_phys_cmd_wait_for_idle( struct dpu_encoder_phys *phys_enc) { @@ -446,42 +304,6 @@ static int _dpu_encoder_phys_cmd_wait_for_idle( return ret; } -static int _dpu_encoder_phys_cmd_wait_for_autorefresh_done( - struct dpu_encoder_phys *phys_enc) -{ - struct dpu_encoder_phys_cmd *cmd_enc = - to_dpu_encoder_phys_cmd(phys_enc); - struct dpu_encoder_wait_info wait_info; - int ret = 0; - - if (!phys_enc) { - DPU_ERROR("invalid encoder\n"); - return -EINVAL; - } - - /* only master deals with autorefresh */ - if (!dpu_encoder_phys_cmd_is_master(phys_enc)) - return 0; - - wait_info.wq = &cmd_enc->autorefresh.kickoff_wq; - wait_info.atomic_cnt = &cmd_enc->autorefresh.kickoff_cnt; - wait_info.timeout_ms = _dpu_encoder_phys_cmd_get_idle_timeout(cmd_enc); - - /* wait for autorefresh kickoff to start */ - ret = dpu_encoder_helper_wait_for_irq(phys_enc, - INTR_IDX_AUTOREFRESH_DONE, &wait_info); - - /* double check that kickoff has started by reading write ptr reg */ - if (!ret) - ret = _dpu_encoder_phys_cmd_poll_write_pointer_started( - phys_enc); - else - dpu_encoder_helper_report_irq_timeout(phys_enc, - INTR_IDX_AUTOREFRESH_DONE); - - return ret; -} - static int dpu_encoder_phys_cmd_control_vblank_irq( struct dpu_encoder_phys *phys_enc, bool enable) @@ -550,20 +372,13 @@ void dpu_encoder_phys_cmd_irq_control(struct dpu_encoder_phys *phys_enc, dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_UNDERRUN); dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, true); - if (dpu_encoder_phys_cmd_is_master(phys_enc)) { + if (dpu_encoder_phys_cmd_is_master(phys_enc)) dpu_encoder_helper_register_irq(phys_enc, INTR_IDX_CTL_START); - dpu_encoder_helper_register_irq(phys_enc, - INTR_IDX_AUTOREFRESH_DONE); - } - } else { - if (dpu_encoder_phys_cmd_is_master(phys_enc)) { + if (dpu_encoder_phys_cmd_is_master(phys_enc)) dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_CTL_START); - dpu_encoder_helper_unregister_irq(phys_enc, - INTR_IDX_AUTOREFRESH_DONE); - } dpu_encoder_helper_unregister_irq(phys_enc, INTR_IDX_UNDERRUN); dpu_encoder_phys_cmd_control_vblank_irq(phys_enc, false); @@ -736,30 +551,6 @@ static void dpu_encoder_phys_cmd_enable(struct dpu_encoder_phys *phys_enc) phys_enc->enable_state = DPU_ENC_ENABLED; } -static bool dpu_encoder_phys_cmd_is_autorefresh_enabled( - struct dpu_encoder_phys *phys_enc) -{ - struct dpu_hw_pingpong *hw_pp; - struct dpu_hw_autorefresh cfg; - int ret; - - if (!phys_enc || !phys_enc->hw_pp) - return 0; - - if (!dpu_encoder_phys_cmd_is_master(phys_enc)) - return 0; - - hw_pp = phys_enc->hw_pp; - if (!hw_pp->ops.get_autorefresh) - return 0; - - ret = hw_pp->ops.get_autorefresh(hw_pp, &cfg); - if (ret) - return 0; - - return cfg.enable; -} - static void _dpu_encoder_phys_cmd_connect_te( struct dpu_encoder_phys *phys_enc, bool enable) { @@ -869,8 +660,7 @@ static void dpu_encoder_phys_cmd_prepare_for_kickoff( DPU_DEBUG_CMDENC(cmd_enc, "pp %d\n", phys_enc->hw_pp->idx - PINGPONG_0); DPU_EVT32(DRMID(phys_enc->parent), phys_enc->hw_pp->idx - PINGPONG_0, - atomic_read(&phys_enc->pending_kickoff_cnt), - atomic_read(&cmd_enc->autorefresh.kickoff_cnt)); + atomic_read(&phys_enc->pending_kickoff_cnt)); /* * Mark kickoff request as outstanding. If there are more than one, @@ -954,10 +744,6 @@ static int dpu_encoder_phys_cmd_wait_for_commit_done( if (dpu_encoder_phys_cmd_is_master(phys_enc)) rc = _dpu_encoder_phys_cmd_wait_for_ctl_start(phys_enc); - if (!rc && dpu_encoder_phys_cmd_is_master(phys_enc) && - cmd_enc->autorefresh.cfg.enable) - rc = _dpu_encoder_phys_cmd_wait_for_autorefresh_done(phys_enc); - /* required for both controllers */ if (!rc && cmd_enc->serialize_wait4pp) dpu_encoder_phys_cmd_prepare_for_kickoff(phys_enc, NULL); @@ -993,58 +779,6 @@ static int dpu_encoder_phys_cmd_wait_for_vblank( return rc; } -static void dpu_encoder_phys_cmd_prepare_commit( - struct dpu_encoder_phys *phys_enc) -{ - struct dpu_encoder_phys_cmd *cmd_enc = - to_dpu_encoder_phys_cmd(phys_enc); - unsigned long lock_flags; - - if (!phys_enc) - return; - - if (!dpu_encoder_phys_cmd_is_master(phys_enc)) - return; - - DPU_EVT32(DRMID(phys_enc->parent), phys_enc->intf_idx - INTF_0, - cmd_enc->autorefresh.cfg.enable); - - if (!dpu_encoder_phys_cmd_is_autorefresh_enabled(phys_enc)) - return; - - /** - * Autorefresh must be disabled carefully: - * - Autorefresh must be disabled between pp_done and te - * signal prior to sdm845 targets. All targets after sdm845 - * supports autorefresh disable without turning off the - * hardware TE and pp_done wait. - * - * - Wait for TX to Complete - * Wait for PPDone confirms the last frame transfer is complete. - * - * - Leave Autorefresh Disabled - * - Assume disable of Autorefresh since it is now safe - * - Can now safely Disable Encoder, do debug printing, etc. - * without worrying that Autorefresh will kickoff - */ - - spin_lock_irqsave(phys_enc->enc_spinlock, lock_flags); - - _dpu_encoder_phys_cmd_config_autorefresh(phys_enc, 0); - - /* check for outstanding TX */ - if (_dpu_encoder_phys_cmd_is_ongoing_pptx(phys_enc)) - atomic_add_unless(&phys_enc->pending_kickoff_cnt, 1, 1); - spin_unlock_irqrestore(phys_enc->enc_spinlock, lock_flags); - - /* wait for ppdone if necessary due to catching ongoing TX */ - if (_dpu_encoder_phys_cmd_wait_for_idle(phys_enc)) - DPU_ERROR_CMDENC(cmd_enc, "pp:%d kickoff timed out\n", - phys_enc->hw_pp->idx - PINGPONG_0); - - DPU_DEBUG_CMDENC(cmd_enc, "disabled autorefresh\n"); -} - static void dpu_encoder_phys_cmd_handle_post_kickoff( struct dpu_encoder_phys *phys_enc) { @@ -1061,27 +795,15 @@ static void dpu_encoder_phys_cmd_handle_post_kickoff( static void dpu_encoder_phys_cmd_trigger_start( struct dpu_encoder_phys *phys_enc) { - struct dpu_encoder_phys_cmd *cmd_enc = - to_dpu_encoder_phys_cmd(phys_enc); - u32 frame_cnt; - if (!phys_enc) return; - /* we don't issue CTL_START when using autorefresh */ - frame_cnt = _dpu_encoder_phys_cmd_get_autorefresh_property(phys_enc); - if (frame_cnt) { - _dpu_encoder_phys_cmd_config_autorefresh(phys_enc, frame_cnt); - atomic_inc(&cmd_enc->autorefresh.kickoff_cnt); - } else { - dpu_encoder_helper_trigger_start(phys_enc); - } + dpu_encoder_helper_trigger_start(phys_enc); } static void dpu_encoder_phys_cmd_init_ops( struct dpu_encoder_phys_ops *ops) { - ops->prepare_commit = dpu_encoder_phys_cmd_prepare_commit; ops->is_master = dpu_encoder_phys_cmd_is_master; ops->mode_set = dpu_encoder_phys_cmd_mode_set; ops->mode_fixup = dpu_encoder_phys_cmd_mode_fixup; @@ -1100,8 +822,6 @@ static void dpu_encoder_phys_cmd_init_ops( ops->irq_control = dpu_encoder_phys_cmd_irq_control; ops->restore = dpu_encoder_phys_cmd_enable_helper; ops->prepare_idle_pc = dpu_encoder_phys_cmd_prepare_idle_pc; - ops->is_autorefresh_enabled = - dpu_encoder_phys_cmd_is_autorefresh_enabled; ops->handle_post_kickoff = dpu_encoder_phys_cmd_handle_post_kickoff; ops->get_line_count = dpu_encoder_phys_cmd_get_line_count; } @@ -1175,20 +895,12 @@ struct dpu_encoder_phys *dpu_encoder_phys_cmd_init( irq->intr_idx = INTR_IDX_UNDERRUN; irq->cb.func = dpu_encoder_phys_cmd_underrun_irq; - irq = &phys_enc->irq[INTR_IDX_AUTOREFRESH_DONE]; - irq->name = "autorefresh_done"; - irq->intr_type = DPU_IRQ_TYPE_PING_PONG_AUTO_REF; - irq->intr_idx = INTR_IDX_AUTOREFRESH_DONE; - irq->cb.func = dpu_encoder_phys_cmd_autorefresh_done_irq; - atomic_set(&phys_enc->vblank_refcount, 0); atomic_set(&phys_enc->pending_kickoff_cnt, 0); atomic_set(&phys_enc->pending_ctlstart_cnt, 0); atomic_set(&cmd_enc->pending_vblank_cnt, 0); init_waitqueue_head(&phys_enc->pending_kickoff_wq); init_waitqueue_head(&cmd_enc->pending_vblank_wq); - atomic_set(&cmd_enc->autorefresh.kickoff_cnt, 0); - init_waitqueue_head(&cmd_enc->autorefresh.kickoff_wq); DPU_DEBUG_CMDENC(cmd_enc, "created\n"); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c index 9308f5c..0bfb511 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c @@ -31,7 +31,6 @@ #define PP_WR_PTR_IRQ 0x024 #define PP_OUT_LINE_COUNT 0x028 #define PP_LINE_COUNT 0x02C -#define PP_AUTOREFRESH_CONFIG 0x030 #define PP_FBC_MODE 0x034 #define PP_FBC_BUDGET_CTL 0x038 @@ -93,44 +92,6 @@ static int dpu_hw_pp_setup_te_config(struct dpu_hw_pingpong *pp, return 0; } -static int dpu_hw_pp_setup_autorefresh_config(struct dpu_hw_pingpong *pp, - struct dpu_hw_autorefresh *cfg) -{ - struct dpu_hw_blk_reg_map *c; - u32 refresh_cfg; - - if (!pp || !cfg) - return -EINVAL; - c = &pp->hw; - - if (cfg->enable) - refresh_cfg = BIT(31) | cfg->frame_count; - else - refresh_cfg = 0; - - DPU_REG_WRITE(c, PP_AUTOREFRESH_CONFIG, refresh_cfg); - DPU_EVT32(pp->idx - PINGPONG_0, refresh_cfg); - - return 0; -} - -static int dpu_hw_pp_get_autorefresh_config(struct dpu_hw_pingpong *pp, - struct dpu_hw_autorefresh *cfg) -{ - struct dpu_hw_blk_reg_map *c; - u32 val; - - if (!pp || !cfg) - return -EINVAL; - - c = &pp->hw; - val = DPU_REG_READ(c, PP_AUTOREFRESH_CONFIG); - cfg->enable = (val & BIT(31)) >> 31; - cfg->frame_count = val & 0xffff; - - return 0; -} - static int dpu_hw_pp_poll_timeout_wr_ptr(struct dpu_hw_pingpong *pp, u32 timeout_us) { @@ -293,8 +254,6 @@ static void _setup_pingpong_ops(struct dpu_hw_pingpong_ops *ops, ops->enable_tearcheck = dpu_hw_pp_enable_te; ops->connect_external_te = dpu_hw_pp_connect_external_te; ops->get_vsync_info = dpu_hw_pp_get_vsync_info; - ops->setup_autorefresh = dpu_hw_pp_setup_autorefresh_config; - ops->get_autorefresh = dpu_hw_pp_get_autorefresh_config; ops->poll_timeout_wr_ptr = dpu_hw_pp_poll_timeout_wr_ptr; ops->get_line_count = dpu_hw_pp_get_line_count; diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h index 93d03cce..7dbfcae 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h @@ -36,11 +36,6 @@ struct dpu_hw_tear_check { u8 hw_vsync_mode; }; -struct dpu_hw_autorefresh { - bool enable; - u32 frame_count; -}; - struct dpu_hw_pp_vsync_info { u32 rd_ptr_init_val; /* value of rd pointer at vsync edge */ u32 rd_ptr_frame_count; /* num frames sent since enabling interface */ @@ -55,7 +50,6 @@ struct dpu_hw_pp_vsync_info { * @setup_tearcheck : program tear check values * @enable_tearcheck : enables tear check * @get_vsync_info : retries timing info of the panel - * @setup_autorefresh : program auto refresh * @setup_dither : function to program the dither hw block * @get_line_count: obtain current vertical line counter */ @@ -88,18 +82,6 @@ struct dpu_hw_pingpong_ops { struct dpu_hw_pp_vsync_info *info); /** - * configure and enable the autorefresh config - */ - int (*setup_autorefresh)(struct dpu_hw_pingpong *pp, - struct dpu_hw_autorefresh *cfg); - - /** - * retrieve autorefresh config from hardware - */ - int (*get_autorefresh)(struct dpu_hw_pingpong *pp, - struct dpu_hw_autorefresh *cfg); - - /** * poll until write pointer transmission starts * @Return: 0 on success, -ETIMEDOUT on timeout */
Remove autorefresh support for smart panels in SDM845 for now. It needs more discussion to figure out the user space communication to set preference for the feature. Signed-off-by: Jeykumar Sankaran <jsanka@codeaurora.org> --- drivers/gpu/drm/msm/disp/dpu1/dpu_connector.c | 7 - drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 37 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_encoder_phys.h | 20 -- .../gpu/drm/msm/disp/dpu1/dpu_encoder_phys_cmd.c | 298 +-------------------- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.c | 41 --- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_pingpong.h | 18 -- 6 files changed, 11 insertions(+), 410 deletions(-)