From patchwork Mon Apr 16 18:22:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jeykumar Sankaran X-Patchwork-Id: 10344493 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id DE8E56039A for ; Tue, 17 Apr 2018 07:42:02 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 9DD41287D0 for ; Tue, 17 Apr 2018 07:42:02 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 8D81428894; Tue, 17 Apr 2018 07:42:02 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 6AFC72887E for ; Tue, 17 Apr 2018 07:41:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id C92DC6E0A2; Tue, 17 Apr 2018 07:41:47 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from smtp.codeaurora.org (smtp.codeaurora.org [198.145.29.96]) by gabe.freedesktop.org (Postfix) with ESMTPS id 88F286E39B; Mon, 16 Apr 2018 18:22:48 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 27377610D8; Mon, 16 Apr 2018 18:22:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1523902967; bh=zSROxoRiKM6/X2DteAi16VUFLDg6vgbv02zbtMv6oEM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=TyGrHJnIfiad8/guAXoxYMpHMrHpzzW6VZK6SKhi3V5PUyf1oNtAzdK6LP60x7tD9 bpELrEcesgeyco6/cJPk3cxcaXoRcl/Hg8SXFX8CORLwKvWT++tA7Im6gCnT9EqhuH 4cLTVEMaog9e9juYKbsklCrvqpTv6c8571RtOQDY= Received: from jeykumar-linux.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jsanka@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id 792BC60FF8; Mon, 16 Apr 2018 18:22:38 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1523902960; bh=zSROxoRiKM6/X2DteAi16VUFLDg6vgbv02zbtMv6oEM=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=ET1zRUMY4bO2FPOqnwnFq7hoSk4ZG8uRGKQGZuFPgBpcp6+R/NjQz4ilnYTUR9FKV YHUKKY00n93K7ZLgDppJgAGc1BiEz6t5PaKXSTpnLiwxERvn/ZQDUOak0PhuHyrBjK j3cZRaiFcHWTmyME7QsjBmO2UiOJ66h0Hg6ucXko= DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org 792BC60FF8 Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jsanka@codeaurora.org From: Jeykumar Sankaran To: dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-arm-msm@vger.kernel.org Subject: [DPU PATCH 6/6] drm/msm: remove dsi-staging driver Date: Mon, 16 Apr 2018 11:22:21 -0700 Message-Id: <1523902941-2253-7-git-send-email-jsanka@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1523902941-2253-1-git-send-email-jsanka@codeaurora.org> References: <1523902941-2253-1-git-send-email-jsanka@codeaurora.org> X-Mailman-Approved-At: Tue, 17 Apr 2018 07:41:47 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hoegsberg@google.com MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP SDM845 has switched from dsi-staging to dsi driver. Removing stale code. Signed-off-by: Jeykumar Sankaran Reviewed-by: Sean Paul --- .../config/arm64/chromiumos-arm64.flavour.config | 1 - .../arm64/chromiumos-qualcomm.flavour.config | 1 - drivers/gpu/drm/msm/Kconfig | 12 - drivers/gpu/drm/msm/Makefile | 21 - drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c | 241 -- drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h | 201 - drivers/gpu/drm/msm/dsi-staging/dsi_clk.h | 276 -- drivers/gpu/drm/msm/dsi-staging/dsi_clk_manager.c | 1235 ------ drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c | 2846 ------------- drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h | 623 --- drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h | 752 ---- drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_1_4.c | 480 --- drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_2_0.c | 234 -- drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_2_2.c | 42 - drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c | 1312 ------ drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_reg.h | 196 - drivers/gpu/drm/msm/dsi-staging/dsi_defs.h | 579 --- drivers/gpu/drm/msm/dsi-staging/dsi_display.c | 4221 -------------------- drivers/gpu/drm/msm/dsi-staging/dsi_display.h | 556 --- drivers/gpu/drm/msm/dsi-staging/dsi_display_test.c | 114 - drivers/gpu/drm/msm/dsi-staging/dsi_display_test.h | 31 - drivers/gpu/drm/msm/dsi-staging/dsi_drm.c | 688 ---- drivers/gpu/drm/msm/dsi-staging/dsi_drm.h | 127 - drivers/gpu/drm/msm/dsi-staging/dsi_hw.h | 48 - drivers/gpu/drm/msm/dsi-staging/dsi_panel.c | 3321 --------------- drivers/gpu/drm/msm/dsi-staging/dsi_panel.h | 257 -- drivers/gpu/drm/msm/dsi-staging/dsi_phy.c | 937 ----- drivers/gpu/drm/msm/dsi-staging/dsi_phy.h | 235 -- drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw.h | 260 -- drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v2_0.c | 252 -- drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v3_0.c | 447 --- .../gpu/drm/msm/dsi-staging/dsi_phy_timing_calc.c | 676 ---- .../gpu/drm/msm/dsi-staging/dsi_phy_timing_calc.h | 144 - .../gpu/drm/msm/dsi-staging/dsi_phy_timing_v2_0.c | 126 - .../gpu/drm/msm/dsi-staging/dsi_phy_timing_v3_0.c | 107 - drivers/gpu/drm/msm/dsi-staging/dsi_pwr.c | 365 -- drivers/gpu/drm/msm/dsi-staging/dsi_pwr.h | 93 - 37 files changed, 22057 deletions(-) delete mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c delete mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h delete mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_clk.h delete mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_clk_manager.c delete mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c delete mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.h delete mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw.h delete mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_1_4.c delete mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_2_0.c delete mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_2_2.c delete mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_hw_cmn.c delete mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_ctrl_reg.h delete mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_defs.h delete mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_display.c delete mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_display.h delete mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_display_test.c delete mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_display_test.h delete mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_drm.c delete mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_drm.h delete mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_hw.h delete mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_panel.c delete mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_panel.h delete mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_phy.c delete mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_phy.h delete mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw.h delete mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v2_0.c delete mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_phy_hw_v3_0.c delete mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_phy_timing_calc.c delete mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_phy_timing_calc.h delete mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_phy_timing_v2_0.c delete mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_phy_timing_v3_0.c delete mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_pwr.c delete mode 100644 drivers/gpu/drm/msm/dsi-staging/dsi_pwr.h diff --git a/chromeos/config/arm64/chromiumos-arm64.flavour.config b/chromeos/config/arm64/chromiumos-arm64.flavour.config index 7b20c8b..dd6767e 100644 --- a/chromeos/config/arm64/chromiumos-arm64.flavour.config +++ b/chromeos/config/arm64/chromiumos-arm64.flavour.config @@ -117,7 +117,6 @@ CONFIG_DRM_MIPI_DSI=y CONFIG_DRM_MSM=y CONFIG_DRM_MSM_DPU=y CONFIG_DRM_MSM_DSI=y -# CONFIG_DRM_MSM_DSI_STAGING is not set # CONFIG_DRM_MSM_HDCP is not set # CONFIG_DRM_MSM_HDMI is not set # CONFIG_DRM_MSM_HDMI_HDCP is not set diff --git a/chromeos/config/arm64/chromiumos-qualcomm.flavour.config b/chromeos/config/arm64/chromiumos-qualcomm.flavour.config index aad22a7..3b38646 100644 --- a/chromeos/config/arm64/chromiumos-qualcomm.flavour.config +++ b/chromeos/config/arm64/chromiumos-qualcomm.flavour.config @@ -30,7 +30,6 @@ CONFIG_DRM_MIPI_DSI=y CONFIG_DRM_MSM=y CONFIG_DRM_MSM_DPU=y CONFIG_DRM_MSM_DSI=y -# CONFIG_DRM_MSM_DSI_STAGING is not set # CONFIG_DRM_MSM_HDCP is not set # CONFIG_DRM_MSM_HDMI is not set # CONFIG_DRM_MSM_HDMI_HDCP is not set diff --git a/drivers/gpu/drm/msm/Kconfig b/drivers/gpu/drm/msm/Kconfig index 5f3bdf0..89e1b82 100644 --- a/drivers/gpu/drm/msm/Kconfig +++ b/drivers/gpu/drm/msm/Kconfig @@ -58,18 +58,6 @@ config DRM_MSM_DSI Choose this option if you have a need for MIPI DSI connector support. -config DRM_MSM_DSI_STAGING - bool "Enable new DSI driver support in MSM DRM driver" - depends on DRM_MSM - select DRM_PANEL - select DRM_MIPI_DSI - default y - help - Choose this option if you need MIPI DSI connector support on MSM - which conforms to DRM. MIPI stands for Mobile Industry Processor - Interface and DSI stands for Display Serial Interface which powers - the primary display of your mobile device. - config DRM_MSM_DSI_PLL bool "Enable DSI PLL driver in MSM DRM" depends on DRM_MSM_DSI && COMMON_CLK diff --git a/drivers/gpu/drm/msm/Makefile b/drivers/gpu/drm/msm/Makefile index a8d8ad9..fee2857 100644 --- a/drivers/gpu/drm/msm/Makefile +++ b/drivers/gpu/drm/msm/Makefile @@ -1,7 +1,6 @@ # SPDX-License-Identifier: GPL-2.0 ccflags-y := -Idrivers/gpu/drm/msm ccflags-y += -Idrivers/gpu/drm/msm/disp/dpu1 -ccflags-y += -Idrivers/gpu/drm/msm/dsi-staging ccflags-$(CONFIG_DRM_MSM_DSI) += -Idrivers/gpu/drm/msm/dsi msm-y := \ @@ -144,26 +143,6 @@ msm-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/phy/dsi_phy_28nm_8960.o msm-$(CONFIG_DRM_MSM_DSI_14NM_PHY) += dsi/phy/dsi_phy_14nm.o msm-$(CONFIG_DRM_MSM_DSI_10NM_PHY) += dsi/phy/dsi_phy_10nm.o -msm-$(CONFIG_DRM_MSM_DSI_STAGING) += dsi-staging/dsi_phy.o \ - dsi-staging/dsi_pwr.o \ - dsi-staging/dsi_phy.o \ - dsi-staging/dsi_phy_hw_v2_0.o \ - dsi-staging/dsi_phy_hw_v3_0.o \ - dsi-staging/dsi_phy_timing_calc.o \ - dsi-staging/dsi_phy_timing_v2_0.o \ - dsi-staging/dsi_phy_timing_v3_0.o \ - dsi-staging/dsi_ctrl_hw_cmn.o \ - dsi-staging/dsi_ctrl_hw_1_4.o \ - dsi-staging/dsi_ctrl_hw_2_0.o \ - dsi-staging/dsi_ctrl_hw_2_2.o \ - dsi-staging/dsi_ctrl.o \ - dsi-staging/dsi_catalog.o \ - dsi-staging/dsi_drm.o \ - dsi-staging/dsi_display.o \ - dsi-staging/dsi_panel.o \ - dsi-staging/dsi_clk_manager.o \ - dsi-staging/dsi_display_test.o - msm-$(CONFIG_DRM_MSM_DSI_28NM_PHY) += dsi/phy/dsi_phy_28nm.o msm-$(CONFIG_DRM_MSM_DSI_20NM_PHY) += dsi/phy/dsi_phy_20nm.o msm-$(CONFIG_DRM_MSM_DSI_28NM_8960_PHY) += dsi/phy/dsi_phy_28nm_8960.o diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c b/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c deleted file mode 100644 index 3cb659a..0000000 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.c +++ /dev/null @@ -1,241 +0,0 @@ -/* - * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#define pr_fmt(fmt) "msm-dsi-catalog:[%s] " fmt, __func__ -#include - -#include "dsi_catalog.h" - -/** - * dsi_catalog_cmn_init() - catalog init for dsi controller v1.4 - */ -static void dsi_catalog_cmn_init(struct dsi_ctrl_hw *ctrl, - enum dsi_ctrl_version version) -{ - /* common functions */ - ctrl->ops.host_setup = dsi_ctrl_hw_cmn_host_setup; - ctrl->ops.video_engine_en = dsi_ctrl_hw_cmn_video_engine_en; - ctrl->ops.video_engine_setup = dsi_ctrl_hw_cmn_video_engine_setup; - ctrl->ops.set_video_timing = dsi_ctrl_hw_cmn_set_video_timing; - ctrl->ops.set_timing_db = dsi_ctrl_hw_cmn_set_timing_db; - ctrl->ops.cmd_engine_setup = dsi_ctrl_hw_cmn_cmd_engine_setup; - ctrl->ops.setup_cmd_stream = dsi_ctrl_hw_cmn_setup_cmd_stream; - ctrl->ops.ctrl_en = dsi_ctrl_hw_cmn_ctrl_en; - ctrl->ops.cmd_engine_en = dsi_ctrl_hw_cmn_cmd_engine_en; - ctrl->ops.phy_sw_reset = dsi_ctrl_hw_cmn_phy_sw_reset; - ctrl->ops.soft_reset = dsi_ctrl_hw_cmn_soft_reset; - ctrl->ops.kickoff_command = dsi_ctrl_hw_cmn_kickoff_command; - ctrl->ops.kickoff_fifo_command = dsi_ctrl_hw_cmn_kickoff_fifo_command; - ctrl->ops.reset_cmd_fifo = dsi_ctrl_hw_cmn_reset_cmd_fifo; - ctrl->ops.trigger_command_dma = dsi_ctrl_hw_cmn_trigger_command_dma; - ctrl->ops.get_interrupt_status = dsi_ctrl_hw_cmn_get_interrupt_status; - ctrl->ops.get_error_status = dsi_ctrl_hw_cmn_get_error_status; - ctrl->ops.clear_error_status = dsi_ctrl_hw_cmn_clear_error_status; - ctrl->ops.clear_interrupt_status = - dsi_ctrl_hw_cmn_clear_interrupt_status; - ctrl->ops.enable_status_interrupts = - dsi_ctrl_hw_cmn_enable_status_interrupts; - ctrl->ops.enable_error_interrupts = - dsi_ctrl_hw_cmn_enable_error_interrupts; - ctrl->ops.video_test_pattern_setup = - dsi_ctrl_hw_cmn_video_test_pattern_setup; - ctrl->ops.cmd_test_pattern_setup = - dsi_ctrl_hw_cmn_cmd_test_pattern_setup; - ctrl->ops.test_pattern_enable = dsi_ctrl_hw_cmn_test_pattern_enable; - ctrl->ops.trigger_cmd_test_pattern = - dsi_ctrl_hw_cmn_trigger_cmd_test_pattern; - ctrl->ops.clear_phy0_ln_err = dsi_ctrl_hw_dln0_phy_err; - ctrl->ops.phy_reset_config = dsi_ctrl_hw_cmn_phy_reset_config; - ctrl->ops.setup_misr = dsi_ctrl_hw_cmn_setup_misr; - ctrl->ops.collect_misr = dsi_ctrl_hw_cmn_collect_misr; - ctrl->ops.debug_bus = dsi_ctrl_hw_cmn_debug_bus; - - switch (version) { - case DSI_CTRL_VERSION_1_4: - ctrl->ops.setup_lane_map = dsi_ctrl_hw_14_setup_lane_map; - ctrl->ops.ulps_ops.ulps_request = dsi_ctrl_hw_14_ulps_request; - ctrl->ops.ulps_ops.ulps_exit = dsi_ctrl_hw_14_ulps_exit; - ctrl->ops.wait_for_lane_idle = - dsi_ctrl_hw_14_wait_for_lane_idle; - ctrl->ops.ulps_ops.get_lanes_in_ulps = - dsi_ctrl_hw_14_get_lanes_in_ulps; - ctrl->ops.clamp_enable = dsi_ctrl_hw_14_clamp_enable; - ctrl->ops.clamp_disable = dsi_ctrl_hw_14_clamp_disable; - ctrl->ops.reg_dump_to_buffer = - dsi_ctrl_hw_14_reg_dump_to_buffer; - break; - case DSI_CTRL_VERSION_2_0: - ctrl->ops.setup_lane_map = dsi_ctrl_hw_20_setup_lane_map; - ctrl->ops.wait_for_lane_idle = - dsi_ctrl_hw_20_wait_for_lane_idle; - ctrl->ops.reg_dump_to_buffer = - dsi_ctrl_hw_20_reg_dump_to_buffer; - ctrl->ops.ulps_ops.ulps_request = NULL; - ctrl->ops.ulps_ops.ulps_exit = NULL; - ctrl->ops.ulps_ops.get_lanes_in_ulps = NULL; - ctrl->ops.clamp_enable = NULL; - ctrl->ops.clamp_disable = NULL; - break; - case DSI_CTRL_VERSION_2_2: - ctrl->ops.phy_reset_config = dsi_ctrl_hw_22_phy_reset_config; - ctrl->ops.setup_lane_map = dsi_ctrl_hw_20_setup_lane_map; - ctrl->ops.wait_for_lane_idle = - dsi_ctrl_hw_20_wait_for_lane_idle; - ctrl->ops.reg_dump_to_buffer = - dsi_ctrl_hw_20_reg_dump_to_buffer; - ctrl->ops.ulps_ops.ulps_request = NULL; - ctrl->ops.ulps_ops.ulps_exit = NULL; - ctrl->ops.ulps_ops.get_lanes_in_ulps = NULL; - ctrl->ops.clamp_enable = NULL; - ctrl->ops.clamp_disable = NULL; - break; - default: - break; - } -} - -/** - * dsi_catalog_ctrl_setup() - return catalog info for dsi controller - * @ctrl: Pointer to DSI controller hw object. - * @version: DSI controller version. - * @index: DSI controller instance ID. - * @phy_isolation_enabled: DSI controller works isolated from phy. - * - * This function setups the catalog information in the dsi_ctrl_hw object. - * - * return: error code for failure and 0 for success. - */ -int dsi_catalog_ctrl_setup(struct dsi_ctrl_hw *ctrl, - enum dsi_ctrl_version version, u32 index, - bool phy_isolation_enabled) -{ - int rc = 0; - - if (version == DSI_CTRL_VERSION_UNKNOWN || - version >= DSI_CTRL_VERSION_MAX) { - pr_err("Unsupported version: %d\n", version); - return -ENOTSUPP; - } - - ctrl->index = index; - set_bit(DSI_CTRL_VIDEO_TPG, ctrl->feature_map); - set_bit(DSI_CTRL_CMD_TPG, ctrl->feature_map); - set_bit(DSI_CTRL_VARIABLE_REFRESH_RATE, ctrl->feature_map); - set_bit(DSI_CTRL_DYNAMIC_REFRESH, ctrl->feature_map); - set_bit(DSI_CTRL_DESKEW_CALIB, ctrl->feature_map); - set_bit(DSI_CTRL_DPHY, ctrl->feature_map); - - switch (version) { - case DSI_CTRL_VERSION_1_4: - dsi_catalog_cmn_init(ctrl, version); - break; - case DSI_CTRL_VERSION_2_0: - case DSI_CTRL_VERSION_2_2: - ctrl->phy_isolation_enabled = phy_isolation_enabled; - dsi_catalog_cmn_init(ctrl, version); - break; - default: - return -ENOTSUPP; - } - - return rc; -} - -/** - * dsi_catalog_phy_2_0_init() - catalog init for DSI PHY 14nm - */ -static void dsi_catalog_phy_2_0_init(struct dsi_phy_hw *phy) -{ - phy->ops.regulator_enable = dsi_phy_hw_v2_0_regulator_enable; - phy->ops.regulator_disable = dsi_phy_hw_v2_0_regulator_disable; - phy->ops.enable = dsi_phy_hw_v2_0_enable; - phy->ops.disable = dsi_phy_hw_v2_0_disable; - phy->ops.calculate_timing_params = - dsi_phy_hw_calculate_timing_params; - phy->ops.phy_idle_on = dsi_phy_hw_v2_0_idle_on; - phy->ops.phy_idle_off = dsi_phy_hw_v2_0_idle_off; - phy->ops.calculate_timing_params = - dsi_phy_hw_calculate_timing_params; - phy->ops.phy_timing_val = dsi_phy_hw_timing_val_v2_0; -} - -/** - * dsi_catalog_phy_3_0_init() - catalog init for DSI PHY 10nm - */ -static void dsi_catalog_phy_3_0_init(struct dsi_phy_hw *phy) -{ - phy->ops.regulator_enable = dsi_phy_hw_v3_0_regulator_enable; - phy->ops.regulator_disable = dsi_phy_hw_v3_0_regulator_disable; - phy->ops.enable = dsi_phy_hw_v3_0_enable; - phy->ops.disable = dsi_phy_hw_v3_0_disable; - phy->ops.calculate_timing_params = - dsi_phy_hw_calculate_timing_params; - phy->ops.ulps_ops.wait_for_lane_idle = - dsi_phy_hw_v3_0_wait_for_lane_idle; - phy->ops.ulps_ops.ulps_request = - dsi_phy_hw_v3_0_ulps_request; - phy->ops.ulps_ops.ulps_exit = - dsi_phy_hw_v3_0_ulps_exit; - phy->ops.ulps_ops.get_lanes_in_ulps = - dsi_phy_hw_v3_0_get_lanes_in_ulps; - phy->ops.ulps_ops.is_lanes_in_ulps = - dsi_phy_hw_v3_0_is_lanes_in_ulps; - phy->ops.phy_timing_val = dsi_phy_hw_timing_val_v3_0; -} - -/** - * dsi_catalog_phy_setup() - return catalog info for dsi phy hardware - * @ctrl: Pointer to DSI PHY hw object. - * @version: DSI PHY version. - * @index: DSI PHY instance ID. - * - * This function setups the catalog information in the dsi_phy_hw object. - * - * return: error code for failure and 0 for success. - */ -int dsi_catalog_phy_setup(struct dsi_phy_hw *phy, - enum dsi_phy_version version, - u32 index) -{ - int rc = 0; - - if (version == DSI_PHY_VERSION_UNKNOWN || - version >= DSI_PHY_VERSION_MAX) { - pr_err("Unsupported version: %d\n", version); - return -ENOTSUPP; - } - - phy->index = index; - set_bit(DSI_PHY_DPHY, phy->feature_map); - - dsi_phy_timing_calc_init(phy, version); - - switch (version) { - case DSI_PHY_VERSION_2_0: - dsi_catalog_phy_2_0_init(phy); - break; - case DSI_PHY_VERSION_3_0: - dsi_catalog_phy_3_0_init(phy); - break; - case DSI_PHY_VERSION_0_0_HPM: - case DSI_PHY_VERSION_0_0_LPM: - case DSI_PHY_VERSION_1_0: - default: - return -ENOTSUPP; - } - - return rc; -} - - diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h b/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h deleted file mode 100644 index 0a46ae0..0000000 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_catalog.h +++ /dev/null @@ -1,201 +0,0 @@ -/* - * Copyright (c) 2015-2018, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef _DSI_CATALOG_H_ -#define _DSI_CATALOG_H_ - -#include "dsi_ctrl_hw.h" -#include "dsi_phy_hw.h" - -/** - * dsi_catalog_ctrl_setup() - return catalog info for dsi controller - * @ctrl: Pointer to DSI controller hw object. - * @version: DSI controller version. - * @index: DSI controller instance ID. - * @phy_isolation_enabled: DSI controller works isolated from phy. - * - * This function setups the catalog information in the dsi_ctrl_hw object. - * - * return: error code for failure and 0 for success. - */ -int dsi_catalog_ctrl_setup(struct dsi_ctrl_hw *ctrl, - enum dsi_ctrl_version version, u32 index, - bool phy_isolation_enabled); - -/** - * dsi_catalog_phy_setup() - return catalog info for dsi phy hardware - * @phy: Pointer to DSI PHY hw object. - * @version: DSI PHY version. - * @index: DSI PHY instance ID. - * - * This function setups the catalog information in the dsi_phy_hw object. - * - * return: error code for failure and 0 for success. - */ -int dsi_catalog_phy_setup(struct dsi_phy_hw *phy, - enum dsi_phy_version version, - u32 index); - -/** - * dsi_phy_timing_calc_init() - initialize info for DSI PHY timing calculations - * @phy: Pointer to DSI PHY hw object. - * @version: DSI PHY version. - * - * This function setups the catalog information in the dsi_phy_hw object. - * - * return: error code for failure and 0 for success. - */ -int dsi_phy_timing_calc_init(struct dsi_phy_hw *phy, - enum dsi_phy_version version); - -/** - * dsi_phy_hw_calculate_timing_params() - DSI PHY timing parameter calculations - * @phy: Pointer to DSI PHY hw object. - * @mode: DSI mode information. - * @host: DSI host configuration. - * @timing: DSI phy lane configurations. - * - * This function setups the catalog information in the dsi_phy_hw object. - * - * return: error code for failure and 0 for success. - */ -int dsi_phy_hw_calculate_timing_params(struct dsi_phy_hw *phy, - struct dsi_mode_info *mode, - struct dsi_host_common_cfg *host, - struct dsi_phy_per_lane_cfgs *timing); - -/* Definitions for 14nm PHY hardware driver */ -void dsi_phy_hw_v2_0_regulator_enable(struct dsi_phy_hw *phy, - struct dsi_phy_per_lane_cfgs *cfg); -void dsi_phy_hw_v2_0_regulator_disable(struct dsi_phy_hw *phy); -void dsi_phy_hw_v2_0_enable(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg); -void dsi_phy_hw_v2_0_disable(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg); -void dsi_phy_hw_v2_0_idle_on(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg); -void dsi_phy_hw_v2_0_idle_off(struct dsi_phy_hw *phy); -int dsi_phy_hw_timing_val_v2_0(struct dsi_phy_per_lane_cfgs *timing_cfg, - u32 *timing_val, u32 size); - -/* Definitions for 10nm PHY hardware driver */ -void dsi_phy_hw_v3_0_regulator_enable(struct dsi_phy_hw *phy, - struct dsi_phy_per_lane_cfgs *cfg); -void dsi_phy_hw_v3_0_regulator_disable(struct dsi_phy_hw *phy); -void dsi_phy_hw_v3_0_enable(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg); -void dsi_phy_hw_v3_0_disable(struct dsi_phy_hw *phy, struct dsi_phy_cfg *cfg); -int dsi_phy_hw_v3_0_wait_for_lane_idle(struct dsi_phy_hw *phy, u32 lanes); -void dsi_phy_hw_v3_0_ulps_request(struct dsi_phy_hw *phy, - struct dsi_phy_cfg *cfg, u32 lanes); -void dsi_phy_hw_v3_0_ulps_exit(struct dsi_phy_hw *phy, - struct dsi_phy_cfg *cfg, u32 lanes); -u32 dsi_phy_hw_v3_0_get_lanes_in_ulps(struct dsi_phy_hw *phy); -bool dsi_phy_hw_v3_0_is_lanes_in_ulps(u32 lanes, u32 ulps_lanes); -int dsi_phy_hw_timing_val_v3_0(struct dsi_phy_per_lane_cfgs *timing_cfg, - u32 *timing_val, u32 size); - -/* DSI controller common ops */ -u32 dsi_ctrl_hw_cmn_get_interrupt_status(struct dsi_ctrl_hw *ctrl); -void dsi_ctrl_hw_cmn_debug_bus(struct dsi_ctrl_hw *ctrl); -void dsi_ctrl_hw_cmn_clear_interrupt_status(struct dsi_ctrl_hw *ctrl, u32 ints); -void dsi_ctrl_hw_cmn_enable_status_interrupts(struct dsi_ctrl_hw *ctrl, - u32 ints); - -u64 dsi_ctrl_hw_cmn_get_error_status(struct dsi_ctrl_hw *ctrl); -void dsi_ctrl_hw_cmn_clear_error_status(struct dsi_ctrl_hw *ctrl, u64 errors); -void dsi_ctrl_hw_cmn_enable_error_interrupts(struct dsi_ctrl_hw *ctrl, - u64 errors); - -void dsi_ctrl_hw_cmn_video_test_pattern_setup(struct dsi_ctrl_hw *ctrl, - enum dsi_test_pattern type, - u32 init_val); -void dsi_ctrl_hw_cmn_cmd_test_pattern_setup(struct dsi_ctrl_hw *ctrl, - enum dsi_test_pattern type, - u32 init_val, - u32 stream_id); -void dsi_ctrl_hw_cmn_test_pattern_enable(struct dsi_ctrl_hw *ctrl, bool enable); -void dsi_ctrl_hw_cmn_trigger_cmd_test_pattern(struct dsi_ctrl_hw *ctrl, - u32 stream_id); - -void dsi_ctrl_hw_cmn_host_setup(struct dsi_ctrl_hw *ctrl, - struct dsi_host_common_cfg *config); -void dsi_ctrl_hw_cmn_video_engine_en(struct dsi_ctrl_hw *ctrl, bool on); -void dsi_ctrl_hw_cmn_video_engine_setup(struct dsi_ctrl_hw *ctrl, - struct dsi_host_common_cfg *common_cfg, - struct dsi_video_engine_cfg *cfg); -void dsi_ctrl_hw_cmn_set_video_timing(struct dsi_ctrl_hw *ctrl, - struct dsi_mode_info *mode); -void dsi_ctrl_hw_cmn_set_timing_db(struct dsi_ctrl_hw *ctrl, - bool enable); -void dsi_ctrl_hw_cmn_cmd_engine_setup(struct dsi_ctrl_hw *ctrl, - struct dsi_host_common_cfg *common_cfg, - struct dsi_cmd_engine_cfg *cfg); - -void dsi_ctrl_hw_cmn_ctrl_en(struct dsi_ctrl_hw *ctrl, bool on); -void dsi_ctrl_hw_cmn_cmd_engine_en(struct dsi_ctrl_hw *ctrl, bool on); - -void dsi_ctrl_hw_cmn_setup_cmd_stream(struct dsi_ctrl_hw *ctrl, - struct dsi_mode_info *mode, - u32 h_stride, - u32 vc_id, - struct dsi_rect *roi); -void dsi_ctrl_hw_cmn_phy_sw_reset(struct dsi_ctrl_hw *ctrl); -void dsi_ctrl_hw_cmn_soft_reset(struct dsi_ctrl_hw *ctrl); - -void dsi_ctrl_hw_cmn_setup_misr(struct dsi_ctrl_hw *ctrl, - enum dsi_op_mode panel_mode, - bool enable, u32 frame_count); -u32 dsi_ctrl_hw_cmn_collect_misr(struct dsi_ctrl_hw *ctrl, - enum dsi_op_mode panel_mode); - -void dsi_ctrl_hw_cmn_kickoff_command(struct dsi_ctrl_hw *ctrl, - struct dsi_ctrl_cmd_dma_info *cmd, - u32 flags); - -void dsi_ctrl_hw_cmn_kickoff_fifo_command(struct dsi_ctrl_hw *ctrl, - struct dsi_ctrl_cmd_dma_fifo_info *cmd, - u32 flags); -void dsi_ctrl_hw_cmn_reset_cmd_fifo(struct dsi_ctrl_hw *ctrl); -void dsi_ctrl_hw_cmn_trigger_command_dma(struct dsi_ctrl_hw *ctrl); -void dsi_ctrl_hw_dln0_phy_err(struct dsi_ctrl_hw *ctrl); -void dsi_ctrl_hw_cmn_phy_reset_config(struct dsi_ctrl_hw *ctrl, - bool enable); -void dsi_ctrl_hw_22_phy_reset_config(struct dsi_ctrl_hw *ctrl, - bool enable); - -/* Definitions specific to 1.4 DSI controller hardware */ -int dsi_ctrl_hw_14_wait_for_lane_idle(struct dsi_ctrl_hw *ctrl, u32 lanes); -void dsi_ctrl_hw_14_setup_lane_map(struct dsi_ctrl_hw *ctrl, - struct dsi_lane_map *lane_map); -void dsi_ctrl_hw_14_ulps_request(struct dsi_ctrl_hw *ctrl, u32 lanes); -void dsi_ctrl_hw_14_ulps_exit(struct dsi_ctrl_hw *ctrl, u32 lanes); -u32 dsi_ctrl_hw_14_get_lanes_in_ulps(struct dsi_ctrl_hw *ctrl); - -void dsi_ctrl_hw_14_clamp_enable(struct dsi_ctrl_hw *ctrl, - u32 lanes, - bool enable_ulps); - -void dsi_ctrl_hw_14_clamp_disable(struct dsi_ctrl_hw *ctrl, - u32 lanes, - bool disable_ulps); -ssize_t dsi_ctrl_hw_14_reg_dump_to_buffer(struct dsi_ctrl_hw *ctrl, - char *buf, - u32 size); - -/* Definitions specific to 2.0 DSI controller hardware */ -void dsi_ctrl_hw_20_setup_lane_map(struct dsi_ctrl_hw *ctrl, - struct dsi_lane_map *lane_map); -int dsi_ctrl_hw_20_wait_for_lane_idle(struct dsi_ctrl_hw *ctrl, u32 lanes); -ssize_t dsi_ctrl_hw_20_reg_dump_to_buffer(struct dsi_ctrl_hw *ctrl, - char *buf, - u32 size); - -#endif /* _DSI_CATALOG_H_ */ diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_clk.h b/drivers/gpu/drm/msm/dsi-staging/dsi_clk.h deleted file mode 100644 index 38fca04..0000000 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_clk.h +++ /dev/null @@ -1,276 +0,0 @@ -/* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#ifndef _DSI_CLK_H_ -#define _DSI_CLK_H_ - -#include -#include -#include -#include -#include "dpu_power_handle.h" - -#define MAX_STRING_LEN 32 -#define MAX_DSI_CTRL 2 - -enum dsi_clk_state { - DSI_CLK_OFF, - DSI_CLK_ON, - DSI_CLK_EARLY_GATE, -}; - -enum clk_req_client { - DSI_CLK_REQ_MDP_CLIENT = 0, - DSI_CLK_REQ_DSI_CLIENT, -}; - -enum dsi_link_clk_type { - DSI_LINK_ESC_CLK, - DSI_LINK_BYTE_CLK, - DSI_LINK_PIX_CLK, - DSI_LINK_BYTE_INTF_CLK, - DSI_LINK_CLK_MAX, -}; - -enum dsi_clk_type { - DSI_CORE_CLK = BIT(0), - DSI_LINK_CLK = BIT(1), - DSI_ALL_CLKS = (BIT(0) | BIT(1)), - DSI_CLKS_MAX = BIT(2), -}; - -struct dsi_clk_ctrl_info { - enum dsi_clk_type clk_type; - enum dsi_clk_state clk_state; - enum clk_req_client client; -}; - -struct clk_ctrl_cb { - void *priv; - int (*dsi_clk_cb)(void *priv, struct dsi_clk_ctrl_info clk_ctrl_info); -}; - -/** - * struct dsi_core_clk_info - Core clock information for DSI hardware - * @mdp_core_clk: Handle to MDP core clock. - * @iface_clk: Handle to MDP interface clock. - * @core_mmss_clk: Handle to MMSS core clock. - * @bus_clk: Handle to bus clock. - * @mnoc_clk: Handle to MMSS NOC clock. - * @dsi_core_client: Pointer to DPU power client - * @phandle: Pointer to DPU power handle - */ -struct dsi_core_clk_info { - struct clk *mdp_core_clk; - struct clk *iface_clk; - struct clk *core_mmss_clk; - struct clk *bus_clk; - struct clk *mnoc_clk; - struct dpu_power_client *dsi_core_client; - struct dpu_power_handle *phandle; -}; - -/** - * struct dsi_link_clk_info - Link clock information for DSI hardware. - * @byte_clk: Handle to DSI byte clock. - * @pixel_clk: Handle to DSI pixel clock. - * @esc_clk: Handle to DSI escape clock. - * @byte_intf_clk: Handle to DSI byte intf. clock. - */ -struct dsi_link_clk_info { - struct clk *byte_clk; - struct clk *pixel_clk; - struct clk *esc_clk; - struct clk *byte_intf_clk; -}; - -/** - * struct link_clk_freq - Clock frequency information for Link clocks - * @byte_clk_rate: Frequency of DSI byte clock in KHz. - * @pixel_clk_rate: Frequency of DSI pixel clock in KHz. - * @esc_clk_rate: Frequency of DSI escape clock in KHz. - */ -struct link_clk_freq { - u32 byte_clk_rate; - u32 pix_clk_rate; - u32 esc_clk_rate; -}; - -/** - * typedef *pre_clockoff_cb() - Callback before clock is turned off - * @priv: private data pointer. - * @clk_type: clock which is being turned off. - * @new_state: next state for the clock. - * - * @return: error code. - */ -typedef int (*pre_clockoff_cb)(void *priv, - enum dsi_clk_type clk_type, - enum dsi_clk_state new_state); - -/** - * typedef *post_clockoff_cb() - Callback after clock is turned off - * @priv: private data pointer. - * @clk_type: clock which was turned off. - * @curr_state: current state for the clock. - * - * @return: error code. - */ -typedef int (*post_clockoff_cb)(void *priv, - enum dsi_clk_type clk_type, - enum dsi_clk_state curr_state); - -/** - * typedef *post_clockon_cb() - Callback after clock is turned on - * @priv: private data pointer. - * @clk_type: clock which was turned on. - * @curr_state: current state for the clock. - * - * @return: error code. - */ -typedef int (*post_clockon_cb)(void *priv, - enum dsi_clk_type clk_type, - enum dsi_clk_state curr_state); - -/** - * typedef *pre_clockon_cb() - Callback before clock is turned on - * @priv: private data pointer. - * @clk_type: clock which is being turned on. - * @new_state: next state for the clock. - * - * @return: error code. - */ -typedef int (*pre_clockon_cb)(void *priv, - enum dsi_clk_type clk_type, - enum dsi_clk_state new_state); - - -/** - * struct dsi_clk_info - clock information for DSI hardware. - * @name: client name. - * @c_clks[MAX_DSI_CTRL] array of core clock configurations - * @l_clks[MAX_DSI_CTRL] array of link clock configurations - * @bus_handle[MAX_DSI_CTRL] array of bus handles - * @ctrl_index[MAX_DSI_CTRL] array of DSI controller indexes mapped - * to core and link clock configurations - * @pre_clkoff_cb callback before clock is turned off - * @post_clkoff_cb callback after clock is turned off - * @post_clkon_cb callback after clock is turned on - * @pre_clkon_cb callback before clock is turned on - * @priv_data pointer to private data - * @master_ndx master DSI controller index - * @dsi_ctrl_count number of DSI controllers - */ -struct dsi_clk_info { - char name[MAX_STRING_LEN]; - struct dsi_core_clk_info c_clks[MAX_DSI_CTRL]; - struct dsi_link_clk_info l_clks[MAX_DSI_CTRL]; - u32 bus_handle[MAX_DSI_CTRL]; - u32 ctrl_index[MAX_DSI_CTRL]; - pre_clockoff_cb pre_clkoff_cb; - post_clockoff_cb post_clkoff_cb; - post_clockon_cb post_clkon_cb; - pre_clockon_cb pre_clkon_cb; - void *priv_data; - u32 master_ndx; - u32 dsi_ctrl_count; -}; - -/** - * struct dsi_clk_link_set - Pair of clock handles to describe link clocks - * @byte_clk: Handle to DSi byte clock. - * @pixel_clk: Handle to DSI pixel clock. - */ -struct dsi_clk_link_set { - struct clk *byte_clk; - struct clk *pixel_clk; -}; - -/** - * dsi_display_clk_mgr_register() - Register DSI clock manager - * @info: Structure containing DSI clock information - */ -void *dsi_display_clk_mngr_register(struct dsi_clk_info *info); - -/** - * dsi_display_clk_mngr_deregister() - Deregister DSI clock manager - * @clk_mngr: DSI clock manager pointer - */ -int dsi_display_clk_mngr_deregister(void *clk_mngr); - -/** - * dsi_register_clk_handle() - Register clock handle with DSI clock manager - * @clk_mngr: DSI clock manager pointer - * @client: DSI clock client pointer. - */ -void *dsi_register_clk_handle(void *clk_mngr, char *client); - -/** - * dsi_deregister_clk_handle() - Deregister clock handle from DSI clock manager - * @client: DSI clock client pointer. - * - * return: error code in case of failure or 0 for success. - */ -int dsi_deregister_clk_handle(void *client); - -/** - * dsi_display_clk_ctrl() - set frequencies for link clks - * @handle: Handle of desired DSI clock client. - * @clk_type: Clock which is being controlled. - * @clk_state: Desired state of clock - * - * return: error code in case of failure or 0 for success. - */ -int dsi_display_clk_ctrl(void *handle, - enum dsi_clk_type clk_type, enum dsi_clk_state clk_state); - -/** - * dsi_clk_set_link_frequencies() - set frequencies for link clks - * @client: DSI clock client pointer. - * @freq: Structure containing link clock frequencies. - * @index: Index of the DSI controller. - * - * return: error code in case of failure or 0 for success. - */ -int dsi_clk_set_link_frequencies(void *client, struct link_clk_freq freq, - u32 index); - - -/** - * dsi_clk_set_pixel_clk_rate() - set frequency for pixel clock - * @client: DSI clock client pointer. - * @pixel_clk: Pixel clock rate in Hz. - * @index: Index of the DSI controller. - * return: error code in case of failure or 0 for success. - */ -int dsi_clk_set_pixel_clk_rate(void *client, u64 pixel_clk, u32 index); - - -/** - * dsi_clk_set_byte_clk_rate() - set frequency for byte clock - * @client: DSI clock client pointer. - * @byte_clk: Pixel clock rate in Hz. - * @index: Index of the DSI controller. - * return: error code in case of failure or 0 for success. - */ -int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk, u32 index); - -/** - * dsi_clk_update_parent() - update parent clocks for specified clock - * @parent: link clock pair which are set as parent. - * @child: link clock pair whose parent has to be set. - */ -int dsi_clk_update_parent(struct dsi_clk_link_set *parent, - struct dsi_clk_link_set *child); -#endif /* _DSI_CLK_H_ */ diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_clk_manager.c b/drivers/gpu/drm/msm/dsi-staging/dsi_clk_manager.c deleted file mode 100644 index 047f759..0000000 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_clk_manager.c +++ /dev/null @@ -1,1235 +0,0 @@ -/* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include -#include -#include -#include "dsi_clk.h" - -#ifdef CONFIG_QCOM_BUS_SCALING -#include -#endif - -struct dsi_core_clks { - struct dsi_core_clk_info clks; - u32 bus_handle; -}; - -struct dsi_link_clks { - struct dsi_link_clk_info clks; - struct link_clk_freq freq; -}; - -struct dsi_clk_mngr { - char name[MAX_STRING_LEN]; - struct mutex clk_mutex; - struct list_head client_list; - - u32 dsi_ctrl_count; - u32 master_ndx; - struct dsi_core_clks core_clks[MAX_DSI_CTRL]; - struct dsi_link_clks link_clks[MAX_DSI_CTRL]; - u32 ctrl_index[MAX_DSI_CTRL]; - u32 core_clk_state; - u32 link_clk_state; - - pre_clockoff_cb pre_clkoff_cb; - post_clockoff_cb post_clkoff_cb; - post_clockon_cb post_clkon_cb; - pre_clockon_cb pre_clkon_cb; - - void *priv_data; -}; - -struct dsi_clk_client_info { - char name[MAX_STRING_LEN]; - u32 core_refcount; - u32 link_refcount; - u32 core_clk_state; - u32 link_clk_state; - struct list_head list; - struct dsi_clk_mngr *mngr; -}; - -static int _get_clk_mngr_index(struct dsi_clk_mngr *mngr, - u32 dsi_ctrl_index, - u32 *clk_mngr_index) -{ - int i; - - for (i = 0; i < mngr->dsi_ctrl_count; i++) { - if (mngr->ctrl_index[i] == dsi_ctrl_index) { - *clk_mngr_index = i; - return 0; - } - } - - return -EINVAL; -} - -/** - * dsi_clk_set_link_frequencies() - set frequencies for link clks - * @clks: Link clock information - * @pixel_clk: pixel clock frequency in KHz. - * @byte_clk: Byte clock frequency in KHz. - * @esc_clk: Escape clock frequency in KHz. - * - * return: error code in case of failure or 0 for success. - */ -int dsi_clk_set_link_frequencies(void *client, struct link_clk_freq freq, - u32 index) -{ - int rc = 0, clk_mngr_index = 0; - struct dsi_clk_client_info *c = client; - struct dsi_clk_mngr *mngr; - - if (!client) { - pr_err("invalid params\n"); - return -EINVAL; - } - - mngr = c->mngr; - rc = _get_clk_mngr_index(mngr, index, &clk_mngr_index); - if (rc) { - pr_err("failed to map control index %d\n", index); - return -EINVAL; - } - - memcpy(&mngr->link_clks[clk_mngr_index].freq, &freq, - sizeof(struct link_clk_freq)); - - return rc; -} - -/** - * dsi_clk_set_pixel_clk_rate() - set frequency for pixel clock - * @clks: DSI link clock information. - * @pixel_clk: Pixel clock rate in KHz. - * - * return: error code in case of failure or 0 for success. - */ -int dsi_clk_set_pixel_clk_rate(void *client, u64 pixel_clk, u32 index) -{ - int rc = 0; - struct dsi_clk_client_info *c = client; - struct dsi_clk_mngr *mngr; - - mngr = c->mngr; - rc = clk_set_rate(mngr->link_clks[index].clks.pixel_clk, pixel_clk); - if (rc) - pr_err("failed to set clk rate for pixel clk, rc=%d\n", rc); - else - mngr->link_clks[index].freq.pix_clk_rate = pixel_clk; - - return rc; -} - -/** - * dsi_clk_set_byte_clk_rate() - set frequency for byte clock - * @client: DSI clock client pointer. - * @byte_clk: Pixel clock rate in Hz. - * @index: Index of the DSI controller. - * return: error code in case of failure or 0 for success. - */ -int dsi_clk_set_byte_clk_rate(void *client, u64 byte_clk, u32 index) -{ - int rc = 0; - struct dsi_clk_client_info *c = client; - struct dsi_clk_mngr *mngr; - - mngr = c->mngr; - rc = clk_set_rate(mngr->link_clks[index].clks.byte_clk, byte_clk); - if (rc) - pr_err("failed to set clk rate for byte clk, rc=%d\n", rc); - else - mngr->link_clks[index].freq.byte_clk_rate = byte_clk; - - return rc; - -} - -/** - * dsi_clk_update_parent() - update parent clocks for specified clock - * @parent: link clock pair which are set as parent. - * @child: link clock pair whose parent has to be set. - */ -int dsi_clk_update_parent(struct dsi_clk_link_set *parent, - struct dsi_clk_link_set *child) -{ - int rc = 0; - - rc = clk_set_parent(child->byte_clk, parent->byte_clk); - if (rc) { - pr_err("failed to set byte clk parent\n"); - goto error; - } - - rc = clk_set_parent(child->pixel_clk, parent->pixel_clk); - if (rc) { - pr_err("failed to set pixel clk parent\n"); - goto error; - } -error: - return rc; -} - -int dsi_core_clk_start(struct dsi_core_clks *c_clks) -{ - int rc = 0; - - if (c_clks->clks.mdp_core_clk) { - rc = clk_prepare_enable(c_clks->clks.mdp_core_clk); - if (rc) { - pr_err("failed to enable mdp_core_clk, rc=%d\n", rc); - goto error; - } - } - - if (c_clks->clks.mnoc_clk) { - rc = clk_prepare_enable(c_clks->clks.mnoc_clk); - if (rc) { - pr_err("failed to enable mnoc_clk, rc=%d\n", rc); - goto error_disable_core_clk; - } - } - - if (c_clks->clks.iface_clk) { - rc = clk_prepare_enable(c_clks->clks.iface_clk); - if (rc) { - pr_err("failed to enable iface_clk, rc=%d\n", rc); - goto error_disable_mnoc_clk; - } - } - - if (c_clks->clks.bus_clk) { - rc = clk_prepare_enable(c_clks->clks.bus_clk); - if (rc) { - pr_err("failed to enable bus_clk, rc=%d\n", rc); - goto error_disable_iface_clk; - } - } - - if (c_clks->clks.core_mmss_clk) { - rc = clk_prepare_enable(c_clks->clks.core_mmss_clk); - if (rc) { - pr_err("failed to enable core_mmss_clk, rc=%d\n", rc); - goto error_disable_bus_clk; - } - } - -#ifdef CONFIG_QCOM_BUS_SCALING - if (c_clks->bus_handle) { - rc = msm_bus_scale_client_update_request(c_clks->bus_handle, 1); - if (rc) { - pr_err("bus scale client enable failed, rc=%d\n", rc); - goto error_disable_mmss_clk; - } - } -#endif - return rc; - -#ifdef CONFIG_QCOM_BUS_SCALING -error_disable_mmss_clk: - if (c_clks->clks.core_mmss_clk) - clk_disable_unprepare(c_clks->clks.core_mmss_clk); -#endif - -error_disable_bus_clk: - if (c_clks->clks.bus_clk) - clk_disable_unprepare(c_clks->clks.bus_clk); -error_disable_iface_clk: - if (c_clks->clks.iface_clk) - clk_disable_unprepare(c_clks->clks.iface_clk); -error_disable_mnoc_clk: - if (c_clks->clks.mnoc_clk) - clk_disable_unprepare(c_clks->clks.mnoc_clk); -error_disable_core_clk: - if (c_clks->clks.mdp_core_clk) - clk_disable_unprepare(c_clks->clks.mdp_core_clk); -error: - return rc; -} - -int dsi_core_clk_stop(struct dsi_core_clks *c_clks) -{ - int rc = 0; - -#ifdef CONFIG_QCOM_BUS_SCALING - if (c_clks->bus_handle) { - rc = msm_bus_scale_client_update_request(c_clks->bus_handle, 0); - if (rc) { - pr_err("bus scale client disable failed, rc=%d\n", rc); - return rc; - } - } -#endif - - if (c_clks->clks.core_mmss_clk) - clk_disable_unprepare(c_clks->clks.core_mmss_clk); - - if (c_clks->clks.bus_clk) - clk_disable_unprepare(c_clks->clks.bus_clk); - - if (c_clks->clks.iface_clk) - clk_disable_unprepare(c_clks->clks.iface_clk); - - if (c_clks->clks.mnoc_clk) - clk_disable_unprepare(c_clks->clks.mnoc_clk); - - if (c_clks->clks.mdp_core_clk) - clk_disable_unprepare(c_clks->clks.mdp_core_clk); - - return rc; -} - -static int dsi_link_clk_set_rate(struct dsi_link_clks *l_clks) -{ - int rc = 0; - - rc = clk_set_rate(l_clks->clks.esc_clk, l_clks->freq.esc_clk_rate); - if (rc) { - pr_err("clk_set_rate failed for esc_clk rc = %d\n", rc); - goto error; - } - - rc = clk_set_rate(l_clks->clks.byte_clk, l_clks->freq.byte_clk_rate); - if (rc) { - pr_err("clk_set_rate failed for byte_clk rc = %d\n", rc); - goto error; - } - - rc = clk_set_rate(l_clks->clks.pixel_clk, l_clks->freq.pix_clk_rate); - if (rc) { - pr_err("clk_set_rate failed for pixel_clk rc = %d\n", rc); - goto error; - } - - /* - * If byte_intf_clk is present, set rate for that too. - * For DPHY: byte_intf_clk_rate = byte_clk_rate / 2 - * todo: this needs to be revisited when support for CPHY is added - */ - if (l_clks->clks.byte_intf_clk) { - rc = clk_set_rate(l_clks->clks.byte_intf_clk, - (l_clks->freq.byte_clk_rate / 2)); - if (rc) { - pr_err("set_rate failed for byte_intf_clk rc = %d\n", - rc); - goto error; - } - } -error: - return rc; -} - -static int dsi_link_clk_prepare(struct dsi_link_clks *l_clks) -{ - int rc = 0; - - rc = clk_prepare(l_clks->clks.esc_clk); - if (rc) { - pr_err("Failed to prepare dsi esc clk, rc=%d\n", rc); - goto esc_clk_err; - } - - rc = clk_prepare(l_clks->clks.byte_clk); - if (rc) { - pr_err("Failed to prepare dsi byte clk, rc=%d\n", rc); - goto byte_clk_err; - } - - rc = clk_prepare(l_clks->clks.pixel_clk); - if (rc) { - pr_err("Failed to prepare dsi pixel clk, rc=%d\n", rc); - goto pixel_clk_err; - } - - if (l_clks->clks.byte_intf_clk) { - rc = clk_prepare(l_clks->clks.byte_intf_clk); - if (rc) { - pr_err("Failed to prepare dsi byte intf clk, rc=%d\n", - rc); - goto byte_intf_clk_err; - } - } - - return rc; - -byte_intf_clk_err: - clk_unprepare(l_clks->clks.pixel_clk); -pixel_clk_err: - clk_unprepare(l_clks->clks.byte_clk); -byte_clk_err: - clk_unprepare(l_clks->clks.esc_clk); -esc_clk_err: - return rc; -} - -static void dsi_link_clk_unprepare(struct dsi_link_clks *l_clks) -{ - if (l_clks->clks.byte_intf_clk) - clk_unprepare(l_clks->clks.byte_intf_clk); - clk_unprepare(l_clks->clks.pixel_clk); - clk_unprepare(l_clks->clks.byte_clk); - clk_unprepare(l_clks->clks.esc_clk); -} - -static int dsi_link_clk_enable(struct dsi_link_clks *l_clks) -{ - int rc = 0; - - rc = clk_enable(l_clks->clks.esc_clk); - if (rc) { - pr_err("Failed to enable dsi esc clk, rc=%d\n", rc); - goto esc_clk_err; - } - - rc = clk_enable(l_clks->clks.byte_clk); - if (rc) { - pr_err("Failed to enable dsi byte clk, rc=%d\n", rc); - goto byte_clk_err; - } - - rc = clk_enable(l_clks->clks.pixel_clk); - if (rc) { - pr_err("Failed to enable dsi pixel clk, rc=%d\n", rc); - goto pixel_clk_err; - } - - if (l_clks->clks.byte_intf_clk) { - rc = clk_enable(l_clks->clks.byte_intf_clk); - if (rc) { - pr_err("Failed to enable dsi byte intf clk, rc=%d\n", - rc); - goto byte_intf_clk_err; - } - } - - return rc; - -byte_intf_clk_err: - clk_disable(l_clks->clks.pixel_clk); -pixel_clk_err: - clk_disable(l_clks->clks.byte_clk); -byte_clk_err: - clk_disable(l_clks->clks.esc_clk); -esc_clk_err: - return rc; -} - -static void dsi_link_clk_disable(struct dsi_link_clks *l_clks) -{ - if (l_clks->clks.byte_intf_clk) - clk_disable(l_clks->clks.byte_intf_clk); - clk_disable(l_clks->clks.esc_clk); - clk_disable(l_clks->clks.pixel_clk); - clk_disable(l_clks->clks.byte_clk); -} - -/** - * dsi_link_clk_start() - enable dsi link clocks - */ -int dsi_link_clk_start(struct dsi_link_clks *clks) -{ - int rc = 0; - - rc = dsi_link_clk_set_rate(clks); - if (rc) { - pr_err("failed to set clk rates, rc = %d\n", rc); - goto error; - } - - rc = dsi_link_clk_prepare(clks); - if (rc) { - pr_err("failed to prepare link clks, rc = %d\n", rc); - goto error; - } - - rc = dsi_link_clk_enable(clks); - if (rc) { - pr_err("failed to enable link clks, rc = %d\n", rc); - goto error_unprepare; - } - - pr_debug("Link clocks are enabled\n"); - return rc; -error_unprepare: - dsi_link_clk_unprepare(clks); -error: - return rc; -} - -/** - * dsi_link_clk_stop() - Stop DSI link clocks. - */ -int dsi_link_clk_stop(struct dsi_link_clks *clks) -{ - dsi_link_clk_disable(clks); - dsi_link_clk_unprepare(clks); - - pr_debug("Link clocks disabled\n"); - - return 0; -} - -static int dsi_display_core_clk_enable(struct dsi_core_clks *clks, - u32 ctrl_count, u32 master_ndx) -{ - int rc = 0; - int i; - struct dsi_core_clks *clk, *m_clks; - - /* - * In case of split DSI usecases, the clock for master controller should - * be enabled before the other controller. Master controller in the - * clock context refers to the controller that sources the clock. - */ - - m_clks = &clks[master_ndx]; - rc = dpu_power_resource_enable(m_clks->clks.phandle, - m_clks->clks.dsi_core_client, true); - - if (rc) { - pr_err("Power resource enable failed, rc=%d\n", rc); - goto error; - } - - rc = dsi_core_clk_start(m_clks); - if (rc) { - pr_err("failed to turn on master clocks, rc=%d\n", rc); - goto error_disable_master_resource; - } - - /* Turn on rest of the core clocks */ - for (i = 0; i < ctrl_count; i++) { - clk = &clks[i]; - if (!clk || (clk == m_clks)) - continue; - - rc = dpu_power_resource_enable(clk->clks.phandle, - clk->clks.dsi_core_client, true); - if (rc) { - pr_err("Power resource enable failed, rc=%d\n", rc); - goto error_disable_master; - } - - rc = dsi_core_clk_start(clk); - if (rc) { - pr_err("failed to turn on clocks, rc=%d\n", rc); - (void)dpu_power_resource_enable(clk->clks.phandle, - clk->clks.dsi_core_client, false); - goto error_disable_master; - } - } - return rc; -error_disable_master: - (void)dsi_core_clk_stop(m_clks); - -error_disable_master_resource: - (void)dpu_power_resource_enable(m_clks->clks.phandle, - m_clks->clks.dsi_core_client, false); -error: - return rc; -} - -static int dsi_display_link_clk_enable(struct dsi_link_clks *clks, - u32 ctrl_count, u32 master_ndx) -{ - int rc = 0; - int i; - struct dsi_link_clks *clk, *m_clks; - - /* - * In case of split DSI usecases, the clock for master controller should - * be enabled before the other controller. Master controller in the - * clock context refers to the controller that sources the clock. - */ - - m_clks = &clks[master_ndx]; - - rc = dsi_link_clk_start(m_clks); - if (rc) { - pr_err("failed to turn on master clocks, rc=%d\n", rc); - goto error; - } - - /* Turn on rest of the core clocks */ - for (i = 0; i < ctrl_count; i++) { - clk = &clks[i]; - if (!clk || (clk == m_clks)) - continue; - - rc = dsi_link_clk_start(clk); - if (rc) { - pr_err("failed to turn on clocks, rc=%d\n", rc); - goto error_disable_master; - } - } - return rc; -error_disable_master: - (void)dsi_link_clk_stop(m_clks); -error: - return rc; -} - -static int dsi_display_core_clk_disable(struct dsi_core_clks *clks, - u32 ctrl_count, u32 master_ndx) -{ - int rc = 0; - int i; - struct dsi_core_clks *clk, *m_clks; - - /* - * In case of split DSI usecases, clock for slave DSI controllers should - * be disabled first before disabling clock for master controller. Slave - * controllers in the clock context refer to controller which source - * clock from another controller. - */ - - m_clks = &clks[master_ndx]; - - /* Turn off non-master core clocks */ - for (i = 0; i < ctrl_count; i++) { - clk = &clks[i]; - if (!clk || (clk == m_clks)) - continue; - - rc = dsi_core_clk_stop(clk); - if (rc) { - pr_debug("failed to turn off clocks, rc=%d\n", rc); - goto error; - } - - rc = dpu_power_resource_enable(clk->clks.phandle, - clk->clks.dsi_core_client, false); - if (rc) { - pr_err("Power resource disable failed: %d\n", rc); - goto error; - } - } - - rc = dsi_core_clk_stop(m_clks); - if (rc) { - pr_err("failed to turn off master clocks, rc=%d\n", rc); - goto error; - } - - rc = dpu_power_resource_enable(m_clks->clks.phandle, - m_clks->clks.dsi_core_client, false); - if (rc) - pr_err("Power resource disable failed: %d\n", rc); -error: - return rc; -} - -static int dsi_display_link_clk_disable(struct dsi_link_clks *clks, - u32 ctrl_count, u32 master_ndx) -{ - int rc = 0; - int i; - struct dsi_link_clks *clk, *m_clks; - - /* - * In case of split DSI usecases, clock for slave DSI controllers should - * be disabled first before disabling clock for master controller. Slave - * controllers in the clock context refer to controller which source - * clock from another controller. - */ - - m_clks = &clks[master_ndx]; - - /* Turn off non-master link clocks */ - for (i = 0; i < ctrl_count; i++) { - clk = &clks[i]; - if (!clk || (clk == m_clks)) - continue; - - rc = dsi_link_clk_stop(clk); - if (rc) - pr_err("failed to turn off clocks, rc=%d\n", rc); - } - - rc = dsi_link_clk_stop(m_clks); - if (rc) - pr_err("failed to turn off master clocks, rc=%d\n", rc); - - return rc; -} - -static int dsi_update_clk_state(struct dsi_core_clks *c_clks, u32 c_state, - struct dsi_link_clks *l_clks, u32 l_state) -{ - int rc = 0; - struct dsi_clk_mngr *mngr; - bool l_c_on = false; - - if (c_clks) { - mngr = - container_of(c_clks, struct dsi_clk_mngr, core_clks[0]); - } else if (l_clks) { - mngr = - container_of(l_clks, struct dsi_clk_mngr, link_clks[0]); - } else { - mngr = NULL; - } - - if (!mngr) - return -EINVAL; - - pr_debug("c_state = %d, l_state = %d\n", - c_clks ? c_state : -1, l_clks ? l_state : -1); - /* - * Below is the sequence to toggle DSI clocks: - * 1. For ON sequence, Core clocks before link clocks - * 2. For OFF sequence, Link clocks before core clocks. - */ - if (c_clks && (c_state == DSI_CLK_ON)) { - if (mngr->core_clk_state == DSI_CLK_OFF) { - rc = mngr->pre_clkon_cb(mngr->priv_data, - DSI_CORE_CLK, - DSI_CLK_ON); - if (rc) { - pr_err("failed to turn on MDP FS rc= %d\n", rc); - goto error; - } - } - rc = dsi_display_core_clk_enable(c_clks, mngr->dsi_ctrl_count, - mngr->master_ndx); - if (rc) { - pr_err("failed to turn on core clks rc = %d\n", rc); - goto error; - } - - if (mngr->post_clkon_cb) { - rc = mngr->post_clkon_cb(mngr->priv_data, - DSI_CORE_CLK, - DSI_CLK_ON); - if (rc) - pr_err("post clk on cb failed, rc = %d\n", rc); - } - mngr->core_clk_state = DSI_CLK_ON; - } - - if (l_clks) { - if (l_state == DSI_CLK_ON) { - if (mngr->pre_clkon_cb) { - rc = mngr->pre_clkon_cb(mngr->priv_data, - DSI_LINK_CLK, l_state); - if (rc) - pr_err("pre link clk on cb failed\n"); - } - rc = dsi_display_link_clk_enable(l_clks, - mngr->dsi_ctrl_count, mngr->master_ndx); - if (rc) { - pr_err("failed to start link clk rc= %d\n", rc); - goto error; - } - if (mngr->post_clkon_cb) { - rc = mngr->post_clkon_cb(mngr->priv_data, - DSI_LINK_CLK, - l_state); - if (rc) - pr_err("post link clk on cb failed\n"); - } - } else { - /* - * Two conditions that need to be checked for Link - * clocks: - * 1. Link clocks need core clocks to be on when - * transitioning from EARLY_GATE to OFF state. - * 2. ULPS mode might have to be enabled in case of OFF - * state. For ULPS, Link clocks should be turned ON - * first before they are turned off again. - * - * If Link is going from EARLY_GATE to OFF state AND - * Core clock is already in EARLY_GATE or OFF state, - * turn on Core clocks and link clocks. - * - * ULPS state is managed as part of the pre_clkoff_cb. - */ - if ((l_state == DSI_CLK_OFF) && - (mngr->link_clk_state == - DSI_CLK_EARLY_GATE) && - (mngr->core_clk_state != - DSI_CLK_ON)) { - rc = dsi_display_core_clk_enable( - mngr->core_clks, mngr->dsi_ctrl_count, - mngr->master_ndx); - if (rc) { - pr_err("core clks did not start\n"); - goto error; - } - - rc = dsi_display_link_clk_enable(l_clks, - mngr->dsi_ctrl_count, mngr->master_ndx); - if (rc) { - pr_err("Link clks did not start\n"); - goto error; - } - l_c_on = true; - pr_debug("ECG: core and Link_on\n"); - } - - if (mngr->pre_clkoff_cb) { - rc = mngr->pre_clkoff_cb(mngr->priv_data, - DSI_LINK_CLK, l_state); - if (rc) - pr_err("pre link clk off cb failed\n"); - } - - rc = dsi_display_link_clk_disable(l_clks, - mngr->dsi_ctrl_count, mngr->master_ndx); - if (rc) { - pr_err("failed to stop link clk, rc = %d\n", - rc); - goto error; - } - - if (mngr->post_clkoff_cb) { - rc = mngr->post_clkoff_cb(mngr->priv_data, - DSI_LINK_CLK, l_state); - if (rc) - pr_err("post link clk off cb failed\n"); - } - /* - * This check is to save unnecessary clock state - * change when going from EARLY_GATE to OFF. In the - * case where the request happens for both Core and Link - * clocks in the same call, core clocks need to be - * turned on first before OFF state can be entered. - * - * Core clocks are turned on here for Link clocks to go - * to OFF state. If core clock request is also present, - * then core clocks can be turned off Core clocks are - * transitioned to OFF state. - */ - if (l_c_on && (!(c_clks && (c_state == DSI_CLK_OFF) - && (mngr->core_clk_state == - DSI_CLK_EARLY_GATE)))) { - rc = dsi_display_core_clk_disable( - mngr->core_clks, mngr->dsi_ctrl_count, - mngr->master_ndx); - if (rc) { - pr_err("core clks did not stop\n"); - goto error; - } - - l_c_on = false; - pr_debug("ECG: core off\n"); - } else - pr_debug("ECG: core off skip\n"); - } - - mngr->link_clk_state = l_state; - } - - if (c_clks && (c_state != DSI_CLK_ON)) { - /* - * When going to OFF state from EARLY GATE state, Core clocks - * should be turned on first so that the IOs can be clamped. - * l_c_on flag is set, then the core clocks were turned before - * to the Link clocks go to OFF state. So Core clocks are - * already ON and this step can be skipped. - * - * IOs are clamped in pre_clkoff_cb callback. - */ - if ((c_state == DSI_CLK_OFF) && - (mngr->core_clk_state == - DSI_CLK_EARLY_GATE) && !l_c_on) { - rc = dsi_display_core_clk_enable(mngr->core_clks, - mngr->dsi_ctrl_count, mngr->master_ndx); - if (rc) { - pr_err("core clks did not start\n"); - goto error; - } - pr_debug("ECG: core on\n"); - } else - pr_debug("ECG: core on skip\n"); - - if (mngr->pre_clkoff_cb) { - rc = mngr->pre_clkoff_cb(mngr->priv_data, - DSI_CORE_CLK, - c_state); - if (rc) - pr_err("pre core clk off cb failed\n"); - } - - rc = dsi_display_core_clk_disable(c_clks, mngr->dsi_ctrl_count, - mngr->master_ndx); - if (rc) { - pr_err("failed to turn off core clks rc = %d\n", rc); - goto error; - } - - if (c_state == DSI_CLK_OFF) { - if (mngr->post_clkoff_cb) { - rc = mngr->post_clkoff_cb(mngr->priv_data, - DSI_CORE_CLK, - DSI_CLK_OFF); - if (rc) - pr_err("post clkoff cb fail, rc = %d\n", - rc); - } - } - mngr->core_clk_state = c_state; - } - -error: - return rc; -} - -static int dsi_recheck_clk_state(struct dsi_clk_mngr *mngr) -{ - int rc = 0; - struct list_head *pos = NULL; - struct dsi_clk_client_info *c; - u32 new_core_clk_state = DSI_CLK_OFF; - u32 new_link_clk_state = DSI_CLK_OFF; - u32 old_c_clk_state = DSI_CLK_OFF; - u32 old_l_clk_state = DSI_CLK_OFF; - struct dsi_core_clks *c_clks = NULL; - struct dsi_link_clks *l_clks = NULL; - - /* - * Conditions to maintain DSI manager clock state based on - * clock states of various clients: - * 1. If any client has clock in ON state, DSI manager clock state - * should be ON. - * 2. If any client is in ECG state with rest of them turned OFF, - * go to Early gate state. - * 3. If all clients have clocks as OFF, then go to OFF state. - */ - list_for_each(pos, &mngr->client_list) { - c = list_entry(pos, struct dsi_clk_client_info, list); - if (c->core_clk_state == DSI_CLK_ON) { - new_core_clk_state = DSI_CLK_ON; - break; - } else if (c->core_clk_state == DSI_CLK_EARLY_GATE) { - new_core_clk_state = DSI_CLK_EARLY_GATE; - } - } - - list_for_each(pos, &mngr->client_list) { - c = list_entry(pos, struct dsi_clk_client_info, list); - if (c->link_clk_state == DSI_CLK_ON) { - new_link_clk_state = DSI_CLK_ON; - break; - } else if (c->link_clk_state == DSI_CLK_EARLY_GATE) { - new_link_clk_state = DSI_CLK_EARLY_GATE; - } - } - - if (new_core_clk_state != mngr->core_clk_state) - c_clks = mngr->core_clks; - - if (new_link_clk_state != mngr->link_clk_state) - l_clks = mngr->link_clks; - - old_c_clk_state = mngr->core_clk_state; - old_l_clk_state = mngr->link_clk_state; - - pr_debug("c_clk_state (%d -> %d)\n", - old_c_clk_state, new_core_clk_state); - pr_debug("l_clk_state (%d -> %d)\n", - old_l_clk_state, new_link_clk_state); - - if (c_clks || l_clks) { - rc = dsi_update_clk_state(c_clks, new_core_clk_state, - l_clks, new_link_clk_state); - if (rc) { - pr_err("failed to update clock state, rc = %d\n", rc); - goto error; - } - } - -error: - return rc; -} - -int dsi_clk_req_state(void *client, enum dsi_clk_type clk, - enum dsi_clk_state state) -{ - int rc = 0; - struct dsi_clk_client_info *c = client; - struct dsi_clk_mngr *mngr; - bool changed = false; - - if (!client || !clk || clk > (DSI_CORE_CLK | DSI_LINK_CLK) || - state > DSI_CLK_EARLY_GATE) { - pr_err("Invalid params, client = %pK, clk = 0x%x, state = %d\n", - client, clk, state); - return -EINVAL; - } - - mngr = c->mngr; - mutex_lock(&mngr->clk_mutex); - - pr_debug("[%s]%s: CLK=%d, new_state=%d, core=%d, linkl=%d\n", - mngr->name, c->name, clk, state, c->core_clk_state, - c->link_clk_state); - - /* - * Clock refcount handling as below: - * i. Increment refcount whenever ON is called. - * ii. Decrement refcount when transitioning from ON state to - * either OFF or EARLY_GATE. - * iii. Do not decrement refcount when changing from - * EARLY_GATE to OFF. - */ - if (state == DSI_CLK_ON) { - if (clk & DSI_CORE_CLK) { - c->core_refcount++; - if (c->core_clk_state != DSI_CLK_ON) { - c->core_clk_state = DSI_CLK_ON; - changed = true; - } - } - if (clk & DSI_LINK_CLK) { - c->link_refcount++; - if (c->link_clk_state != DSI_CLK_ON) { - c->link_clk_state = DSI_CLK_ON; - changed = true; - } - } - } else if ((state == DSI_CLK_EARLY_GATE) || - (state == DSI_CLK_OFF)) { - if (clk & DSI_CORE_CLK) { - if (c->core_refcount == 0) { - if ((c->core_clk_state == - DSI_CLK_EARLY_GATE) && - (state == DSI_CLK_OFF)) { - changed = true; - c->core_clk_state = DSI_CLK_OFF; - } else { - pr_warn("Core refcount is zero for %s", - c->name); - } - } else { - c->core_refcount--; - if (c->core_refcount == 0) { - c->core_clk_state = state; - changed = true; - } - } - } - if (clk & DSI_LINK_CLK) { - if (c->link_refcount == 0) { - if ((c->link_clk_state == - DSI_CLK_EARLY_GATE) && - (state == DSI_CLK_OFF)) { - changed = true; - c->link_clk_state = DSI_CLK_OFF; - } else { - pr_warn("Link refcount is zero for %s", - c->name); - } - } else { - c->link_refcount--; - if (c->link_refcount == 0) { - c->link_clk_state = state; - changed = true; - } - } - } - } - pr_debug("[%s]%s: change=%d, Core (ref=%d, state=%d), Link (ref=%d, state=%d)\n", - mngr->name, c->name, changed, c->core_refcount, - c->core_clk_state, c->link_refcount, c->link_clk_state); - - if (changed) { - rc = dsi_recheck_clk_state(mngr); - if (rc) - pr_err("Failed to adjust clock state rc = %d\n", rc); - } - - mutex_unlock(&mngr->clk_mutex); - return rc; -} - -DEFINE_MUTEX(dsi_mngr_clk_mutex); - -int dsi_display_clk_ctrl(void *handle, - enum dsi_clk_type clk_type, enum dsi_clk_state clk_state) -{ - int rc = 0; - - if (!handle) { - pr_err("%s: Invalid arg\n", __func__); - return -EINVAL; - } - - mutex_lock(&dsi_mngr_clk_mutex); - rc = dsi_clk_req_state(handle, clk_type, clk_state); - if (rc) - pr_err("%s: failed set clk state, rc = %d\n", __func__, rc); - mutex_unlock(&dsi_mngr_clk_mutex); - - return rc; -} - -void *dsi_register_clk_handle(void *clk_mngr, char *client) -{ - void *handle = NULL; - struct dsi_clk_mngr *mngr = clk_mngr; - struct dsi_clk_client_info *c; - - if (!mngr) { - pr_err("bad params\n"); - return ERR_PTR(-EINVAL); - } - - mutex_lock(&mngr->clk_mutex); - - c = kzalloc(sizeof(*c), GFP_KERNEL); - if (!c) { - handle = ERR_PTR(-ENOMEM); - goto error; - } - - strlcpy(c->name, client, MAX_STRING_LEN); - c->mngr = mngr; - - list_add(&c->list, &mngr->client_list); - - pr_debug("[%s]: Added new client (%s)\n", mngr->name, c->name); - handle = c; -error: - mutex_unlock(&mngr->clk_mutex); - return handle; -} - -int dsi_deregister_clk_handle(void *client) -{ - int rc = 0; - struct dsi_clk_client_info *c = client; - struct dsi_clk_mngr *mngr; - struct list_head *pos = NULL; - struct list_head *tmp = NULL; - struct dsi_clk_client_info *node = NULL; - - if (!client) { - pr_err("Invalid params\n"); - return -EINVAL; - } - - mngr = c->mngr; - pr_debug("%s: ENTER\n", mngr->name); - mutex_lock(&mngr->clk_mutex); - c->core_clk_state = DSI_CLK_OFF; - c->link_clk_state = DSI_CLK_OFF; - - rc = dsi_recheck_clk_state(mngr); - if (rc) { - pr_err("clock state recheck failed rc = %d\n", rc); - goto error; - } - - list_for_each_safe(pos, tmp, &mngr->client_list) { - node = list_entry(pos, struct dsi_clk_client_info, - list); - if (node == c) { - list_del(&node->list); - pr_debug("Removed device (%s)\n", node->name); - kfree(node); - break; - } - } - -error: - mutex_unlock(&mngr->clk_mutex); - pr_debug("%s: EXIT, rc = %d\n", mngr->name, rc); - return rc; -} - -void *dsi_display_clk_mngr_register(struct dsi_clk_info *info) -{ - struct dsi_clk_mngr *mngr; - int i = 0; - - if (!info) { - pr_err("Invalid params\n"); - return ERR_PTR(-EINVAL); - } - - mngr = kzalloc(sizeof(*mngr), GFP_KERNEL); - if (!mngr) { - mngr = ERR_PTR(-ENOMEM); - goto error; - } - - mutex_init(&mngr->clk_mutex); - mngr->dsi_ctrl_count = info->dsi_ctrl_count; - mngr->master_ndx = info->master_ndx; - - if (mngr->dsi_ctrl_count > MAX_DSI_CTRL) { - kfree(mngr); - return ERR_PTR(-EINVAL); - } - - for (i = 0; i < mngr->dsi_ctrl_count; i++) { - memcpy(&mngr->core_clks[i].clks, &info->c_clks[i], - sizeof(struct dsi_core_clk_info)); - memcpy(&mngr->link_clks[i].clks, &info->l_clks[i], - sizeof(struct dsi_link_clk_info)); - mngr->core_clks[i].bus_handle = info->bus_handle[i]; - mngr->ctrl_index[i] = info->ctrl_index[i]; - } - - INIT_LIST_HEAD(&mngr->client_list); - mngr->pre_clkon_cb = info->pre_clkon_cb; - mngr->post_clkon_cb = info->post_clkon_cb; - mngr->pre_clkoff_cb = info->pre_clkoff_cb; - mngr->post_clkoff_cb = info->post_clkoff_cb; - mngr->priv_data = info->priv_data; - memcpy(mngr->name, info->name, MAX_STRING_LEN); - -error: - pr_debug("EXIT, rc = %ld\n", PTR_ERR(mngr)); - return mngr; -} - -int dsi_display_clk_mngr_deregister(void *clk_mngr) -{ - int rc = 0; - struct dsi_clk_mngr *mngr = clk_mngr; - struct list_head *position = NULL; - struct list_head *tmp = NULL; - struct dsi_clk_client_info *node = NULL; - - if (!mngr) { - pr_err("Invalid params\n"); - return -EINVAL; - } - - pr_debug("%s: ENTER\n", mngr->name); - mutex_lock(&mngr->clk_mutex); - - list_for_each_safe(position, tmp, &mngr->client_list) { - node = list_entry(position, struct dsi_clk_client_info, - list); - list_del(&node->list); - pr_debug("Removed device (%s)\n", node->name); - kfree(node); - } - - rc = dsi_recheck_clk_state(mngr); - if (rc) - pr_err("failed to disable all clocks\n"); - - mutex_unlock(&mngr->clk_mutex); - pr_debug("%s: EXIT, rc = %d\n", mngr->name, rc); - kfree(mngr); - return rc; -} - diff --git a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c b/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c deleted file mode 100644 index c0cf9ca..0000000 --- a/drivers/gpu/drm/msm/dsi-staging/dsi_ctrl.c +++ /dev/null @@ -1,2846 +0,0 @@ -/* - * Copyright (c) 2016-2018, The Linux Foundation. All rights reserved. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 and - * only version 2 as published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#define pr_fmt(fmt) "dsi-ctrl:[%s] " fmt, __func__ - -#include -#include -#include -#include -#ifdef CONFIG_QCOM_BUS_SCALING -#include -#endif -#include -#include