From patchwork Wed Jun 20 12:50:16 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sravanthi Kollukuduru X-Patchwork-Id: 10477377 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D399160383 for ; Wed, 20 Jun 2018 12:50:47 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id BFEC628C8A for ; Wed, 20 Jun 2018 12:50:47 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B3E2D28E41; Wed, 20 Jun 2018 12:50:47 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7DE6628C8A for ; Wed, 20 Jun 2018 12:50:45 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 4C8316E1D3; Wed, 20 Jun 2018 12:50:41 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from smtp.codeaurora.org (smtp.codeaurora.org [198.145.29.96]) by gabe.freedesktop.org (Postfix) with ESMTPS id D0F496E195; Wed, 20 Jun 2018 12:50:39 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1000) id BBF3760B13; Wed, 20 Jun 2018 12:50:39 +0000 (UTC) Received: from skolluku-linux.qualcomm.com (blr-c-bdr-fw-01_globalnat_allzones-outside.qualcomm.com [103.229.19.19]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: skolluku@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id AF3CC60B16; Wed, 20 Jun 2018 12:50:32 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org AF3CC60B16 From: Sravanthi Kollukuduru To: dri-devel@lists.freedesktop.org, linux-arm-msm@vger.kernel.org, freedreno@lists.freedesktop.org Subject: [DPU PATCH 1/5] drm/msm/dpu: remove smart dma support Date: Wed, 20 Jun 2018 18:20:16 +0530 Message-Id: <1529499020-8499-2-git-send-email-skolluku@codeaurora.org> X-Mailer: git-send-email 1.9.1 In-Reply-To: <1529499020-8499-1-git-send-email-skolluku@codeaurora.org> References: <1529499020-8499-1-git-send-email-skolluku@codeaurora.org> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: hoegsberg@chromium.org, Sravanthi Kollukuduru MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Removing the smart dma feature implementation as it is currently not enabled on dpu driver. Signed-off-by: Sravanthi Kollukuduru --- drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 51 +---- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c | 25 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h | 19 -- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c | 76 ++----- drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h | 4 - drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c | 159 +++------------ drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h | 56 +----- drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c | 26 +-- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 265 ++----------------------- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h | 38 +--- drivers/gpu/drm/msm/msm_drv.h | 2 +- 11 files changed, 84 insertions(+), 637 deletions(-) diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c index 6c78c11c3..f0aafec 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c @@ -230,12 +230,9 @@ static void _dpu_crtc_blend_setup_mixer(struct drm_crtc *crtc, stage_idx = zpos_cnt[pstate->stage]++; stage_cfg->stage[pstate->stage][stage_idx] = dpu_plane_pipe(plane); - stage_cfg->multirect_index[pstate->stage][stage_idx] = - pstate->multirect_index; DPU_EVT32(DRMID(crtc), DRMID(plane), stage_idx, dpu_plane_pipe(plane) - SSPP_VIG0, pstate->stage, - pstate->multirect_index, pstate->multirect_mode, format->base.pixel_format, fb ? fb->modifier : 0); /* blend config update */ @@ -1334,14 +1331,13 @@ struct plane_state { struct dpu_plane_state *dpu_pstate; const struct drm_plane_state *drm_pstate; int stage; - u32 pipe_id; }; static int dpu_crtc_atomic_check(struct drm_crtc *crtc, struct drm_crtc_state *state) { struct dpu_crtc *dpu_crtc; - struct plane_state pstates[DPU_STAGE_MAX * 4]; + struct plane_state pstates[DPU_STAGE_MAX * 2]; struct dpu_crtc_state *cstate; const struct drm_plane_state *pstate; @@ -1351,10 +1347,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, struct dpu_private_state *dpu_priv_state; int cnt = 0, rc = 0, mixer_width, i, z_pos; - - struct dpu_multirect_plane_states multirect_plane[DPU_STAGE_MAX * 2]; - int multirect_count = 0; - const struct drm_plane_state *pipe_staged[SSPP_MAX]; int left_zpos_cnt = 0, right_zpos_cnt = 0; if (!crtc) { @@ -1378,8 +1370,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, if (state->active_changed) state->mode_changed = true; - memset(pipe_staged, 0, sizeof(pipe_staged)); - mixer_width = dpu_crtc_get_mixer_width(dpu_crtc, cstate, mode); _dpu_crtc_setup_lm_bounds(crtc, state); @@ -1398,18 +1388,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, pstates[cnt].dpu_pstate = to_dpu_plane_state(pstate); pstates[cnt].drm_pstate = pstate; pstates[cnt].stage = pstate->normalized_zpos; - pstates[cnt].pipe_id = dpu_plane_pipe(plane); - - if (pipe_staged[pstates[cnt].pipe_id]) { - multirect_plane[multirect_count].r0 = - pipe_staged[pstates[cnt].pipe_id]; - multirect_plane[multirect_count].r1 = pstate; - multirect_count++; - - pipe_staged[pstates[cnt].pipe_id] = NULL; - } else { - pipe_staged[pstates[cnt].pipe_id] = pstate; - } cnt++; @@ -1426,20 +1404,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, } } - for (i = 1; i < SSPP_MAX; i++) { - if (pipe_staged[i]) { - dpu_plane_clear_multirect(pipe_staged[i]); - - if (is_dpu_plane_virtual(pipe_staged[i]->plane)) { - DPU_ERROR( - "r1 only virt plane:%d not supported\n", - pipe_staged[i]->plane->base.id); - rc = -EINVAL; - goto end; - } - } - } - z_pos = -1; for (i = 0; i < cnt; i++) { /* reset counts at every new blend stage */ @@ -1478,17 +1442,6 @@ static int dpu_crtc_atomic_check(struct drm_crtc *crtc, DPU_DEBUG("%s: zpos %d", dpu_crtc->name, z_pos); } - for (i = 0; i < multirect_count; i++) { - if (dpu_plane_validate_multirect_v2(&multirect_plane[i])) { - DPU_ERROR( - "multirect validation failed for planes (%d - %d)\n", - multirect_plane[i].r0->plane->base.id, - multirect_plane[i].r1->plane->base.id); - rc = -EINVAL; - goto end; - } - } - rc = dpu_core_perf_crtc_check(crtc, state); if (rc) { DPU_ERROR("crtc%d failed performance check %d\n", @@ -1708,8 +1661,6 @@ static int _dpu_debugfs_status_show(struct seq_file *s, void *data) seq_printf(s, "\tdst x:%4d dst_y:%4d dst_w:%4d dst_h:%4d\n", state->crtc_x, state->crtc_y, state->crtc_w, state->crtc_h); - seq_printf(s, "\tmultirect: mode: %d index: %d\n", - pstate->multirect_mode, pstate->multirect_index); seq_puts(s, "\n"); } diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c index ab46bf6..f0c2881 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.c @@ -58,7 +58,6 @@ .max_mixer_width = DEFAULT_DPU_OUTPUT_LINE_WIDTH, .max_mixer_blendstages = 0xb, .qseed_type = DPU_SSPP_SCALER_QSEED3, - .smart_dma_rev = DPU_SSPP_SMART_DMA_V2, .ubwc_version = DPU_HW_UBWC_VER_20, .has_src_split = true, .has_dim_layer = true, @@ -134,12 +133,11 @@ .maxvdeciexp = MAX_VERT_DECIMATION, }; -#define _VIG_SBLK(num, sdma_pri) \ +#define _VIG_SBLK(num) \ { \ .common = &sdm845_sspp_common, \ .maxdwnscale = MAX_DOWNSCALE_RATIO, \ .maxupscale = MAX_UPSCALE_RATIO, \ - .smart_dma_priority = sdma_pri, \ .src_blk = {.name = STRCAT("sspp_src_", num), \ .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \ .scaler_blk = {.name = STRCAT("sspp_scaler", num), \ @@ -149,30 +147,27 @@ .id = DPU_SSPP_CSC_10BIT, \ .base = 0x1a00, .len = 0x100,}, \ .format_list = plane_formats_yuv, \ - .virt_format_list = plane_formats, \ } -#define _DMA_SBLK(num, sdma_pri) \ +#define _DMA_SBLK(num) \ { \ .common = &sdm845_sspp_common, \ .maxdwnscale = SSPP_UNITY_SCALE, \ .maxupscale = SSPP_UNITY_SCALE, \ - .smart_dma_priority = sdma_pri, \ .src_blk = {.name = STRCAT("sspp_src_", num), \ .id = DPU_SSPP_SRC, .base = 0x00, .len = 0x150,}, \ .format_list = plane_formats, \ - .virt_format_list = plane_formats, \ } -static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 = _VIG_SBLK("0", 5); -static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 = _VIG_SBLK("1", 6); -static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 = _VIG_SBLK("2", 7); -static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 = _VIG_SBLK("3", 8); +static const struct dpu_sspp_sub_blks sdm845_vig_sblk_0 = _VIG_SBLK("0"); +static const struct dpu_sspp_sub_blks sdm845_vig_sblk_1 = _VIG_SBLK("1"); +static const struct dpu_sspp_sub_blks sdm845_vig_sblk_2 = _VIG_SBLK("2"); +static const struct dpu_sspp_sub_blks sdm845_vig_sblk_3 = _VIG_SBLK("3"); -static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK("8", 1); -static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9", 2); -static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK("10", 3); -static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11", 4); +static const struct dpu_sspp_sub_blks sdm845_dma_sblk_0 = _DMA_SBLK("8"); +static const struct dpu_sspp_sub_blks sdm845_dma_sblk_1 = _DMA_SBLK("9"); +static const struct dpu_sspp_sub_blks sdm845_dma_sblk_2 = _DMA_SBLK("10"); +static const struct dpu_sspp_sub_blks sdm845_dma_sblk_3 = _DMA_SBLK("11"); #define SSPP_VIG_BLK(_name, _id, _base, _sblk, _xinid, _clkctrl) \ { \ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h index f0cb0d4..1b04448 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_catalog.h @@ -108,8 +108,6 @@ enum { * @DPU_SSPP_QOS, SSPP support QoS control, danger/safe/creq * @DPU_SSPP_QOS_8LVL, SSPP support 8-level QoS control * @DPU_SSPP_EXCL_RECT, SSPP supports exclusion rect - * @DPU_SSPP_SMART_DMA_V1, SmartDMA 1.0 support - * @DPU_SSPP_SMART_DMA_V2, SmartDMA 2.0 support * @DPU_SSPP_TS_PREFILL Supports prefill with traffic shaper * @DPU_SSPP_TS_PREFILL_REC1 Supports prefill with traffic shaper multirec * @DPU_SSPP_CDP Supports client driven prefetch @@ -126,8 +124,6 @@ enum { DPU_SSPP_QOS, DPU_SSPP_QOS_8LVL, DPU_SSPP_EXCL_RECT, - DPU_SSPP_SMART_DMA_V1, - DPU_SSPP_SMART_DMA_V2, DPU_SSPP_TS_PREFILL, DPU_SSPP_TS_PREFILL_REC1, DPU_SSPP_CDP, @@ -298,7 +294,6 @@ struct dpu_qos_lut_tbl { * @max_mixer_blendstages max layer mixer blend stages or * supported z order * @qseed_type qseed2 or qseed3 support. - * @smart_dma_rev Supported version of SmartDMA feature. * @ubwc_version UBWC feature version (0x0 for not supported) * @has_src_split source split feature status * @has_dim_layer dim layer feature status @@ -308,7 +303,6 @@ struct dpu_caps { u32 max_mixer_width; u32 max_mixer_blendstages; u32 qseed_type; - u32 smart_dma_rev; u32 ubwc_version; bool has_src_split; bool has_dim_layer; @@ -338,7 +332,6 @@ struct dpu_sspp_blks_common { * @danger_vblank: danger priority during vertical blanking * @maxdwnscale: max downscale ratio supported(without DECIMATION) * @maxupscale: maxupscale ratio supported - * @smart_dma_priority: hw priority of rect1 of multirect pipe * @max_per_pipe_bw: maximum allowable bandwidth of this pipe in kBps * @src_blk: * @scaler_blk: @@ -348,7 +341,6 @@ struct dpu_sspp_blks_common { * @pcc_blk: * @igc_blk: * @format_list: Pointer to list of supported formats - * @virt_format_list: Pointer to list of supported formats for virtual planes */ struct dpu_sspp_sub_blks { const struct dpu_sspp_blks_common *common; @@ -356,7 +348,6 @@ struct dpu_sspp_sub_blks { u32 danger_vblank; u32 maxdwnscale; u32 maxupscale; - u32 smart_dma_priority; u32 max_per_pipe_bw; struct dpu_src_blk src_blk; struct dpu_scaler_blk scaler_blk; @@ -367,7 +358,6 @@ struct dpu_sspp_sub_blks { struct dpu_pp_blk igc_blk; const struct dpu_format_extended *format_list; - const struct dpu_format_extended *virt_format_list; }; /** @@ -792,13 +782,4 @@ struct dpu_mdss_hw_cfg_handler { */ void dpu_hw_catalog_deinit(struct dpu_mdss_cfg *dpu_cfg); -/** - * dpu_hw_sspp_multirect_enabled - check multirect enabled for the sspp - * @cfg: pointer to sspp cfg - */ -static inline bool dpu_hw_sspp_multirect_enabled(const struct dpu_sspp_cfg *cfg) -{ - return test_bit(DPU_SSPP_SMART_DMA_V1, &cfg->features) || - test_bit(DPU_SSPP_SMART_DMA_V2, &cfg->features); -} #endif /* _DPU_HW_CATALOG_H */ diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c index ad02316..1b9f41f 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.c @@ -22,8 +22,7 @@ (0x40 + (((lm) - LM_0) * 0x004)) #define CTL_LAYER_EXT2(lm) \ (0x70 + (((lm) - LM_0) * 0x004)) -#define CTL_LAYER_EXT3(lm) \ - (0xA0 + (((lm) - LM_0) * 0x004)) + #define CTL_TOP 0x014 #define CTL_FLUSH 0x018 #define CTL_START 0x01C @@ -299,7 +298,6 @@ static void dpu_hw_ctl_clear_all_blendstages(struct dpu_hw_ctl *ctx) DPU_REG_WRITE(c, CTL_LAYER(LM_0 + i), 0); DPU_REG_WRITE(c, CTL_LAYER_EXT(LM_0 + i), 0); DPU_REG_WRITE(c, CTL_LAYER_EXT2(LM_0 + i), 0); - DPU_REG_WRITE(c, CTL_LAYER_EXT3(LM_0 + i), 0); } } @@ -307,8 +305,8 @@ static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_ctl *ctx, enum dpu_lm lm, struct dpu_hw_stage_cfg *stage_cfg) { struct dpu_hw_blk_reg_map *c = &ctx->hw; - u32 mixercfg = 0, mixercfg_ext = 0, mix, ext; - u32 mixercfg_ext2 = 0, mixercfg_ext3 = 0; + u32 mixercfg = 0, mixercfg_ext = 0, mixercfg_ext2 = 0; + u32 mix, ext; int i, j; u8 stages; int pipes_per_stage; @@ -334,41 +332,22 @@ static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_ctl *ctx, ext = i >= 7; for (j = 0 ; j < pipes_per_stage; j++) { - enum dpu_sspp_multirect_index rect_index = - stage_cfg->multirect_index[i][j]; - switch (stage_cfg->stage[i][j]) { case SSPP_VIG0: - if (rect_index == DPU_SSPP_RECT_1) { - mixercfg_ext3 |= ((i + 1) & 0xF) << 0; - } else { - mixercfg |= mix << 0; - mixercfg_ext |= ext << 0; - } + mixercfg |= mix << 0; + mixercfg_ext |= ext << 0; break; case SSPP_VIG1: - if (rect_index == DPU_SSPP_RECT_1) { - mixercfg_ext3 |= ((i + 1) & 0xF) << 4; - } else { - mixercfg |= mix << 3; - mixercfg_ext |= ext << 2; - } + mixercfg |= mix << 3; + mixercfg_ext |= ext << 2; break; case SSPP_VIG2: - if (rect_index == DPU_SSPP_RECT_1) { - mixercfg_ext3 |= ((i + 1) & 0xF) << 8; - } else { - mixercfg |= mix << 6; - mixercfg_ext |= ext << 4; - } + mixercfg |= mix << 6; + mixercfg_ext |= ext << 4; break; case SSPP_VIG3: - if (rect_index == DPU_SSPP_RECT_1) { - mixercfg_ext3 |= ((i + 1) & 0xF) << 12; - } else { - mixercfg |= mix << 26; - mixercfg_ext |= ext << 6; - } + mixercfg |= mix << 26; + mixercfg_ext |= ext << 6; break; case SSPP_RGB0: mixercfg |= mix << 9; @@ -387,36 +366,20 @@ static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_ctl *ctx, mixercfg_ext |= ext << 14; break; case SSPP_DMA0: - if (rect_index == DPU_SSPP_RECT_1) { - mixercfg_ext2 |= ((i + 1) & 0xF) << 8; - } else { - mixercfg |= mix << 18; - mixercfg_ext |= ext << 16; - } + mixercfg |= mix << 18; + mixercfg_ext |= ext << 16; break; case SSPP_DMA1: - if (rect_index == DPU_SSPP_RECT_1) { - mixercfg_ext2 |= ((i + 1) & 0xF) << 12; - } else { - mixercfg |= mix << 21; - mixercfg_ext |= ext << 18; - } + mixercfg |= mix << 21; + mixercfg_ext |= ext << 18; break; case SSPP_DMA2: - if (rect_index == DPU_SSPP_RECT_1) { - mixercfg_ext2 |= ((i + 1) & 0xF) << 16; - } else { - mix |= (i + 1) & 0xF; - mixercfg_ext2 |= mix << 0; - } + mix |= (i + 1) & 0xF; + mixercfg_ext2 |= mix << 0; break; case SSPP_DMA3: - if (rect_index == DPU_SSPP_RECT_1) { - mixercfg_ext2 |= ((i + 1) & 0xF) << 20; - } else { - mix |= (i + 1) & 0xF; - mixercfg_ext2 |= mix << 4; - } + mix |= (i + 1) & 0xF; + mixercfg_ext2 |= mix << 4; break; case SSPP_CURSOR0: mixercfg_ext |= ((i + 1) & 0xF) << 20; @@ -434,7 +397,6 @@ static void dpu_hw_ctl_setup_blendstage(struct dpu_hw_ctl *ctx, DPU_REG_WRITE(c, CTL_LAYER(lm), mixercfg); DPU_REG_WRITE(c, CTL_LAYER_EXT(lm), mixercfg_ext); DPU_REG_WRITE(c, CTL_LAYER_EXT2(lm), mixercfg_ext2); - DPU_REG_WRITE(c, CTL_LAYER_EXT3(lm), mixercfg_ext3); } static void dpu_hw_ctl_intf_cfg(struct dpu_hw_ctl *ctx, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h index c66a71f..729fc10 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_ctl.h @@ -16,7 +16,6 @@ #include "dpu_hw_mdss.h" #include "dpu_hw_util.h" #include "dpu_hw_catalog.h" -#include "dpu_hw_sspp.h" #include "dpu_hw_blk.h" /** @@ -33,12 +32,9 @@ enum dpu_ctl_mode_sel { /** * struct dpu_hw_stage_cfg - blending stage cfg * @stage : SSPP_ID at each stage - * @multirect_index: index of the rectangle of SSPP. */ struct dpu_hw_stage_cfg { enum dpu_sspp stage[DPU_STAGE_MAX][PIPES_PER_STAGE]; - enum dpu_sspp_multirect_index multirect_index - [DPU_STAGE_MAX][PIPES_PER_STAGE]; }; /** diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c index 6640906..197fed1 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.c @@ -34,19 +34,6 @@ #define SSPP_SRC_UNPACK_PATTERN 0x34 #define SSPP_SRC_OP_MODE 0x38 -/* SSPP_MULTIRECT*/ -#define SSPP_SRC_SIZE_REC1 0x16C -#define SSPP_SRC_XY_REC1 0x168 -#define SSPP_OUT_SIZE_REC1 0x160 -#define SSPP_OUT_XY_REC1 0x164 -#define SSPP_SRC_FORMAT_REC1 0x174 -#define SSPP_SRC_UNPACK_PATTERN_REC1 0x178 -#define SSPP_SRC_OP_MODE_REC1 0x17C -#define SSPP_MULTIRECT_OPMODE 0x170 -#define SSPP_SRC_CONSTANT_COLOR_REC1 0x180 -#define SSPP_EXCL_REC_SIZE_REC1 0x184 -#define SSPP_EXCL_REC_XY_REC1 0x188 - #define MDSS_MDP_OP_DEINTERLACE BIT(22) #define MDSS_MDP_OP_DEINTERLACE_ODD BIT(23) #define MDSS_MDP_OP_IGC_ROM_1 BIT(18) @@ -171,35 +158,6 @@ static inline int _sspp_subblk_offset(struct dpu_hw_pipe *ctx, return rc; } -static void dpu_hw_sspp_setup_multirect(struct dpu_hw_pipe *ctx, - enum dpu_sspp_multirect_index index, - enum dpu_sspp_multirect_mode mode) -{ - u32 mode_mask; - u32 idx; - - if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) - return; - - if (index == DPU_SSPP_RECT_SOLO) { - /** - * if rect index is RECT_SOLO, we cannot expect a - * virtual plane sharing the same SSPP id. So we go - * and disable multirect - */ - mode_mask = 0; - } else { - mode_mask = DPU_REG_READ(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx); - mode_mask |= index; - if (mode == DPU_SSPP_MULTIRECT_TIME_MX) - mode_mask |= BIT(2); - else - mode_mask &= ~BIT(2); - } - - DPU_REG_WRITE(&ctx->hw, SSPP_MULTIRECT_OPMODE + idx, mode_mask); -} - static void _sspp_setup_opmode(struct dpu_hw_pipe *ctx, u32 mask, u8 en) { @@ -243,31 +201,19 @@ static void _sspp_setup_csc10_opmode(struct dpu_hw_pipe *ctx, * Setup source pixel format, flip, */ static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx, - const struct dpu_format *fmt, u32 flags, - enum dpu_sspp_multirect_index rect_mode) + const struct dpu_format *fmt, u32 flags) { struct dpu_hw_blk_reg_map *c; u32 chroma_samp, unpack, src_format; u32 opmode = 0; u32 fast_clear = 0; - u32 op_mode_off, unpack_pat_off, format_off; u32 idx; if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx) || !fmt) return; - if (rect_mode == DPU_SSPP_RECT_SOLO || rect_mode == DPU_SSPP_RECT_0) { - op_mode_off = SSPP_SRC_OP_MODE; - unpack_pat_off = SSPP_SRC_UNPACK_PATTERN; - format_off = SSPP_SRC_FORMAT; - } else { - op_mode_off = SSPP_SRC_OP_MODE_REC1; - unpack_pat_off = SSPP_SRC_UNPACK_PATTERN_REC1; - format_off = SSPP_SRC_FORMAT_REC1; - } - c = &ctx->hw; - opmode = DPU_REG_READ(c, op_mode_off + idx); + opmode = DPU_REG_READ(c, SSPP_SRC_OP_MODE + idx); opmode &= ~(MDSS_MDP_OP_FLIP_LR | MDSS_MDP_OP_FLIP_UD | MDSS_MDP_OP_BWC_EN | MDSS_MDP_OP_PE_OVERRIDE); @@ -337,9 +283,9 @@ static void dpu_hw_sspp_setup_format(struct dpu_hw_pipe *ctx, VIG_CSC_10_EN | VIG_CSC_10_SRC_DATAFMT, DPU_FORMAT_IS_YUV(fmt)); - DPU_REG_WRITE(c, format_off + idx, src_format); - DPU_REG_WRITE(c, unpack_pat_off + idx, unpack); - DPU_REG_WRITE(c, op_mode_off + idx, opmode); + DPU_REG_WRITE(c, SSPP_SRC_FORMAT + idx, src_format); + DPU_REG_WRITE(c, SSPP_SRC_UNPACK_PATTERN + idx, unpack); + DPU_REG_WRITE(c, SSPP_SRC_OP_MODE + idx, opmode); /* clear previous UBWC error */ DPU_REG_WRITE(c, SSPP_UBWC_ERROR_STATUS + idx, BIT(31)); @@ -435,12 +381,10 @@ static u32 _dpu_hw_sspp_get_scaler3_ver(struct dpu_hw_pipe *ctx) * dpu_hw_sspp_setup_rects() */ static void dpu_hw_sspp_setup_rects(struct dpu_hw_pipe *ctx, - struct dpu_hw_pipe_cfg *cfg, - enum dpu_sspp_multirect_index rect_index) + struct dpu_hw_pipe_cfg *cfg) { struct dpu_hw_blk_reg_map *c; u32 src_size, src_xy, dst_size, dst_xy, ystride0, ystride1; - u32 src_size_off, src_xy_off, out_size_off, out_xy_off; u32 idx; if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx) || !cfg) @@ -448,62 +392,29 @@ static void dpu_hw_sspp_setup_rects(struct dpu_hw_pipe *ctx, c = &ctx->hw; - if (rect_index == DPU_SSPP_RECT_SOLO || rect_index == DPU_SSPP_RECT_0) { - src_size_off = SSPP_SRC_SIZE; - src_xy_off = SSPP_SRC_XY; - out_size_off = SSPP_OUT_SIZE; - out_xy_off = SSPP_OUT_XY; - } else { - src_size_off = SSPP_SRC_SIZE_REC1; - src_xy_off = SSPP_SRC_XY_REC1; - out_size_off = SSPP_OUT_SIZE_REC1; - out_xy_off = SSPP_OUT_XY_REC1; - } - - /* src and dest rect programming */ src_xy = (cfg->src_rect.y << 16) | (cfg->src_rect.x); src_size = (cfg->src_rect.h << 16) | (cfg->src_rect.w); dst_xy = (cfg->dst_rect.y << 16) | (cfg->dst_rect.x); dst_size = (cfg->dst_rect.h << 16) | (cfg->dst_rect.w); - if (rect_index == DPU_SSPP_RECT_SOLO) { - ystride0 = (cfg->layout.plane_pitch[0]) | + ystride0 = (cfg->layout.plane_pitch[0]) | (cfg->layout.plane_pitch[1] << 16); - ystride1 = (cfg->layout.plane_pitch[2]) | + ystride1 = (cfg->layout.plane_pitch[2]) | (cfg->layout.plane_pitch[3] << 16); - } else { - ystride0 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE0 + idx); - ystride1 = DPU_REG_READ(c, SSPP_SRC_YSTRIDE1 + idx); - - if (rect_index == DPU_SSPP_RECT_0) { - ystride0 = (ystride0 & 0xFFFF0000) | - (cfg->layout.plane_pitch[0] & 0x0000FFFF); - ystride1 = (ystride1 & 0xFFFF0000)| - (cfg->layout.plane_pitch[2] & 0x0000FFFF); - } else { - ystride0 = (ystride0 & 0x0000FFFF) | - ((cfg->layout.plane_pitch[0] << 16) & - 0xFFFF0000); - ystride1 = (ystride1 & 0x0000FFFF) | - ((cfg->layout.plane_pitch[2] << 16) & - 0xFFFF0000); - } - } /* rectangle register programming */ - DPU_REG_WRITE(c, src_size_off + idx, src_size); - DPU_REG_WRITE(c, src_xy_off + idx, src_xy); - DPU_REG_WRITE(c, out_size_off + idx, dst_size); - DPU_REG_WRITE(c, out_xy_off + idx, dst_xy); + DPU_REG_WRITE(c, SSPP_SRC_SIZE + idx, src_size); + DPU_REG_WRITE(c, SSPP_SRC_XY + idx, src_xy); + DPU_REG_WRITE(c, SSPP_OUT_SIZE + idx, dst_size); + DPU_REG_WRITE(c, SSPP_OUT_XY + idx, dst_xy); DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE0 + idx, ystride0); DPU_REG_WRITE(c, SSPP_SRC_YSTRIDE1 + idx, ystride1); } static void dpu_hw_sspp_setup_sourceaddress(struct dpu_hw_pipe *ctx, - struct dpu_hw_pipe_cfg *cfg, - enum dpu_sspp_multirect_index rect_mode) + struct dpu_hw_pipe_cfg *cfg) { int i; u32 idx; @@ -511,21 +422,9 @@ static void dpu_hw_sspp_setup_sourceaddress(struct dpu_hw_pipe *ctx, if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) return; - if (rect_mode == DPU_SSPP_RECT_SOLO) { - for (i = 0; i < ARRAY_SIZE(cfg->layout.plane_addr); i++) - DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx + i * 0x4, - cfg->layout.plane_addr[i]); - } else if (rect_mode == DPU_SSPP_RECT_0) { - DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx, - cfg->layout.plane_addr[0]); - DPU_REG_WRITE(&ctx->hw, SSPP_SRC2_ADDR + idx, - cfg->layout.plane_addr[2]); - } else { - DPU_REG_WRITE(&ctx->hw, SSPP_SRC1_ADDR + idx, - cfg->layout.plane_addr[0]); - DPU_REG_WRITE(&ctx->hw, SSPP_SRC3_ADDR + idx, - cfg->layout.plane_addr[2]); - } + for (i = 0; i < ARRAY_SIZE(cfg->layout.plane_addr); i++) + DPU_REG_WRITE(&ctx->hw, SSPP_SRC0_ADDR + idx + i * 0x4, + cfg->layout.plane_addr[i]); } static void dpu_hw_sspp_setup_csc(struct dpu_hw_pipe *ctx, @@ -545,19 +444,14 @@ static void dpu_hw_sspp_setup_csc(struct dpu_hw_pipe *ctx, dpu_hw_csc_setup(&ctx->hw, idx, data, csc10); } -static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_pipe *ctx, u32 color, enum - dpu_sspp_multirect_index rect_index) +static void dpu_hw_sspp_setup_solidfill(struct dpu_hw_pipe *ctx, u32 color) { u32 idx; if (_sspp_subblk_offset(ctx, DPU_SSPP_SRC, &idx)) return; - if (rect_index == DPU_SSPP_RECT_SOLO || rect_index == DPU_SSPP_RECT_0) - DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR + idx, color); - else - DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR_REC1 + idx, - color); + DPU_REG_WRITE(&ctx->hw, SSPP_SRC_CONSTANT_COLOR + idx, color); } static void dpu_hw_sspp_setup_danger_safe_lut(struct dpu_hw_pipe *ctx, @@ -660,9 +554,6 @@ static void _setup_layer_ops(struct dpu_hw_pipe *c, test_bit(DPU_SSPP_CSC_10BIT, &features)) c->ops.setup_csc = dpu_hw_sspp_setup_csc; - if (dpu_hw_sspp_multirect_enabled(c->cap)) - c->ops.setup_multirect = dpu_hw_sspp_setup_multirect; - if (test_bit(DPU_SSPP_SCALER_QSEED3, &features)) { c->ops.setup_scaler = _dpu_hw_sspp_setup_scaler3; c->ops.get_scaler_ver = _dpu_hw_sspp_get_scaler3_ver; @@ -701,8 +592,7 @@ static struct dpu_sspp_cfg *_sspp_offset(enum dpu_sspp sspp, }; struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, - void __iomem *addr, struct dpu_mdss_cfg *catalog, - bool is_virtual_pipe) + void __iomem *addr, struct dpu_mdss_cfg *catalog) { struct dpu_hw_pipe *hw_pipe; struct dpu_sspp_cfg *cfg; @@ -734,13 +624,12 @@ struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, goto blk_init_error; } - if (!is_virtual_pipe) - dpu_dbg_reg_register_dump_range(DPU_DBG_NAME, cfg->name, - hw_pipe->hw.blk_off, - hw_pipe->hw.blk_off + hw_pipe->hw.length, - hw_pipe->hw.xin_id); + dpu_dbg_reg_register_dump_range(DPU_DBG_NAME, cfg->name, + hw_pipe->hw.blk_off, + hw_pipe->hw.blk_off + hw_pipe->hw.length, + hw_pipe->hw.xin_id); - if (cfg->sblk->scaler_blk.len && !is_virtual_pipe) + if (cfg->sblk->scaler_blk.len) dpu_dbg_reg_register_dump_range(DPU_DBG_NAME, cfg->sblk->scaler_blk.name, hw_pipe->hw.blk_off + cfg->sblk->scaler_blk.base, diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h index 0bb5ecb..b11a9d86 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_hw_sspp.h @@ -49,28 +49,6 @@ enum { DPU_SSPP_COMP_MAX }; -/** - * DPU_SSPP_RECT_SOLO - multirect disabled - * DPU_SSPP_RECT_0 - rect0 of a multirect pipe - * DPU_SSPP_RECT_1 - rect1 of a multirect pipe - * - * Note: HW supports multirect with either RECT0 or - * RECT1. Considering no benefit of such configs over - * SOLO mode and to keep the plane management simple, - * we dont support single rect multirect configs. - */ -enum dpu_sspp_multirect_index { - DPU_SSPP_RECT_SOLO = 0, - DPU_SSPP_RECT_0, - DPU_SSPP_RECT_1, -}; - -enum dpu_sspp_multirect_mode { - DPU_SSPP_MULTIRECT_NONE = 0, - DPU_SSPP_MULTIRECT_PARALLEL, - DPU_SSPP_MULTIRECT_TIME_MX, -}; - enum { DPU_FRAME_LINEAR, DPU_FRAME_TILE_A4X, @@ -159,15 +137,11 @@ struct dpu_hw_pixel_ext { * @src_rect: src ROI, caller takes into account the different operations * such as decimation, flip etc to program this field * @dest_rect: destination ROI. - * @index: index of the rectangle of SSPP - * @mode: parallel or time multiplex multirect mode */ struct dpu_hw_pipe_cfg { struct dpu_hw_fmt_layout layout; struct dpu_rect src_rect; struct dpu_rect dst_rect; - enum dpu_sspp_multirect_index index; - enum dpu_sspp_multirect_mode mode; }; /** @@ -235,21 +209,17 @@ struct dpu_hw_sspp_ops { * @ctx: Pointer to pipe context * @cfg: Pointer to pipe config structure * @flags: Extra flags for format config - * @index: rectangle index in multirect */ void (*setup_format)(struct dpu_hw_pipe *ctx, - const struct dpu_format *fmt, u32 flags, - enum dpu_sspp_multirect_index index); + const struct dpu_format *fmt, u32 flags); /** * setup_rects - setup pipe ROI rectangles * @ctx: Pointer to pipe context * @cfg: Pointer to pipe config structure - * @index: rectangle index in multirect */ void (*setup_rects)(struct dpu_hw_pipe *ctx, - struct dpu_hw_pipe_cfg *cfg, - enum dpu_sspp_multirect_index index); + struct dpu_hw_pipe_cfg *cfg); /** * setup_pe - setup pipe pixel extension @@ -263,11 +233,9 @@ struct dpu_hw_sspp_ops { * setup_sourceaddress - setup pipe source addresses * @ctx: Pointer to pipe context * @cfg: Pointer to pipe config structure - * @index: rectangle index in multirect */ void (*setup_sourceaddress)(struct dpu_hw_pipe *ctx, - struct dpu_hw_pipe_cfg *cfg, - enum dpu_sspp_multirect_index index); + struct dpu_hw_pipe_cfg *cfg); /** * setup_csc - setup color space coversion @@ -281,21 +249,8 @@ struct dpu_hw_sspp_ops { * @ctx: Pointer to pipe context * @const_color: Fill color value * @flags: Pipe flags - * @index: rectangle index in multirect - */ - void (*setup_solidfill)(struct dpu_hw_pipe *ctx, u32 color, - enum dpu_sspp_multirect_index index); - - /** - * setup_multirect - setup multirect configuration - * @ctx: Pointer to pipe context - * @index: rectangle index in multirect - * @mode: parallel fetch / time multiplex multirect mode */ - - void (*setup_multirect)(struct dpu_hw_pipe *ctx, - enum dpu_sspp_multirect_index index, - enum dpu_sspp_multirect_mode mode); + void (*setup_solidfill)(struct dpu_hw_pipe *ctx, u32 color); /** * setup_sharpening - setup sharpening @@ -410,8 +365,7 @@ static inline struct dpu_hw_pipe *to_dpu_hw_pipe(struct dpu_hw_blk *hw) * @is_virtual_pipe: is this pipe virtual pipe */ struct dpu_hw_pipe *dpu_hw_sspp_init(enum dpu_sspp idx, - void __iomem *addr, struct dpu_mdss_cfg *catalog, - bool is_virtual_pipe); + void __iomem *addr, struct dpu_mdss_cfg *catalog); /** * dpu_hw_sspp_destroy(): Destroys SSPP driver context diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c index 8bd1224..3b17a02 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c @@ -596,10 +596,6 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms) int primary_planes_idx = 0, i, ret; int max_crtc_count; - u32 sspp_id[MAX_PLANES]; - u32 master_plane_id[MAX_PLANES]; - u32 num_virt_planes = 0; - if (!dpu_kms || !dpu_kms->dev || !dpu_kms->dev->dev) { DPU_ERROR("invalid dpu_kms\n"); return -EINVAL; @@ -626,7 +622,7 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms) primary = false; plane = dpu_plane_init(dev, catalog->sspp[i].id, primary, - (1UL << max_crtc_count) - 1, 0); + (1UL << max_crtc_count) - 1); if (IS_ERR(plane)) { DPU_ERROR("dpu_plane_init failed\n"); ret = PTR_ERR(plane); @@ -637,26 +633,6 @@ static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms) if (primary) primary_planes[primary_planes_idx++] = plane; - if (dpu_hw_sspp_multirect_enabled(&catalog->sspp[i]) && - dpu_is_custom_client()) { - int priority = - catalog->sspp[i].sblk->smart_dma_priority; - sspp_id[priority - 1] = catalog->sspp[i].id; - master_plane_id[priority - 1] = plane->base.id; - num_virt_planes++; - } - } - - /* Initialize smart DMA virtual planes */ - for (i = 0; i < num_virt_planes; i++) { - plane = dpu_plane_init(dev, sspp_id[i], false, - (1UL << max_crtc_count) - 1, master_plane_id[i]); - if (IS_ERR(plane)) { - DPU_ERROR("dpu_plane for virtual SSPP init failed\n"); - ret = PTR_ERR(plane); - goto fail; - } - priv->planes[priv->num_planes++] = plane; } max_crtc_count = min(max_crtc_count, primary_planes_idx); diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 6090ace..0fd05de 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -60,13 +60,6 @@ #define DPU_PLANE_COLOR_FILL_FLAG BIT(31) #define DPU_ZPOS_MAX 255 -/* multirect rect index */ -enum { - R0, - R1, - R_MAX -}; - #define DPU_QSEED3_DEFAULT_PRELOAD_H 0x4 #define DPU_QSEED3_DEFAULT_PRELOAD_V 0x3 @@ -90,7 +83,6 @@ enum dpu_plane_qos { * struct dpu_plane - local dpu plane structure * @aspace: address space pointer * @csc_ptr: Points to dpu_csc_cfg structure to use for current - * @mplane_list: List of multirect planes of the same pipe * @catalog: Points to dpu catalog structure * @revalidate: force revalidation of all the plane properties */ @@ -110,8 +102,6 @@ struct dpu_plane { uint32_t color_fill; bool is_error; bool is_rt_pipe; - bool is_virtual; - struct list_head mplane_list; struct dpu_mdss_cfg *catalog; struct dpu_csc_cfg *csc_ptr; @@ -161,7 +151,7 @@ static bool dpu_plane_sspp_enabled(struct drm_plane_state *state) static inline int _dpu_plane_calc_fill_level(struct drm_plane *plane, const struct dpu_format *fmt, u32 src_width) { - struct dpu_plane *pdpu, *tmp; + struct dpu_plane *pdpu; struct dpu_plane_state *pstate; u32 fixed_buff_size; u32 total_fl; @@ -175,15 +165,6 @@ static inline int _dpu_plane_calc_fill_level(struct drm_plane *plane, pstate = to_dpu_plane_state(plane->state); fixed_buff_size = pdpu->pipe_sblk->common->pixel_ram_size; - list_for_each_entry(tmp, &pdpu->mplane_list, mplane_list) { - if (!dpu_plane_enabled(tmp->base.state)) - continue; - DPU_DEBUG("plane%d/%d src_width:%d/%d\n", - pdpu->base.base.id, tmp->base.base.id, - src_width, tmp->pipe_cfg.src_rect.w); - src_width = max_t(u32, src_width, tmp->pipe_cfg.src_rect.w); - } - if (fmt->fetch_planes == DPU_PLANE_PSEUDO_PLANAR) { if (fmt->chroma_sample == DPU_CHROMA_420) { /* NV12 */ @@ -195,13 +176,8 @@ static inline int _dpu_plane_calc_fill_level(struct drm_plane *plane, ((src_width + 32) * fmt->bpp); } } else { - if (pstate->multirect_mode == DPU_SSPP_MULTIRECT_PARALLEL) { - total_fl = (fixed_buff_size / 2) * 2 / - ((src_width + 32) * fmt->bpp); - } else { total_fl = (fixed_buff_size) * 2 / ((src_width + 32) * fmt->bpp); - } } DPU_DEBUG("plane%u: pnum:%d fmt: %4.4s w:%u fl:%u\n", @@ -619,10 +595,8 @@ static inline void _dpu_plane_set_scanout(struct drm_plane *plane, pipe_cfg->layout.plane_addr[2], pipe_cfg->layout.plane_size[2], pipe_cfg->layout.plane_addr[3], - pipe_cfg->layout.plane_size[3], - pstate->multirect_index); - pdpu->pipe_hw->ops.setup_sourceaddress(pdpu->pipe_hw, pipe_cfg, - pstate->multirect_index); + pipe_cfg->layout.plane_size[3]); + pdpu->pipe_hw->ops.setup_sourceaddress(pdpu->pipe_hw, pipe_cfg); } } @@ -812,8 +786,7 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu, /* update sspp */ if (fmt && pdpu->pipe_hw->ops.setup_solidfill) { pdpu->pipe_hw->ops.setup_solidfill(pdpu->pipe_hw, - (color & 0xFFFFFF) | ((alpha & 0xFF) << 24), - pstate->multirect_index); + (color & 0xFFFFFF) | ((alpha & 0xFF) << 24)); /* override scaler/decimation if solid fill */ pdpu->pipe_cfg.src_rect.x = 0; @@ -824,20 +797,17 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu, if (pdpu->pipe_hw->ops.setup_format) pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, - fmt, DPU_SSPP_SOLID_FILL, - pstate->multirect_index); + fmt, DPU_SSPP_SOLID_FILL); if (pdpu->pipe_hw->ops.setup_rects) pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw, - &pdpu->pipe_cfg, - pstate->multirect_index); + &pdpu->pipe_cfg); if (pdpu->pipe_hw->ops.setup_pe) pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw, &pstate->pixel_ext); - if (pdpu->pipe_hw->ops.setup_scaler && - pstate->multirect_index != DPU_SSPP_RECT_1) + if (pdpu->pipe_hw->ops.setup_scaler) pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw, &pdpu->pipe_cfg, &pstate->pixel_ext, &pstate->scaler3_cfg); @@ -846,133 +816,6 @@ static int _dpu_plane_color_fill(struct dpu_plane *pdpu, return 0; } -void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state) -{ - struct dpu_plane_state *pstate; - - if (!drm_state) - return; - - pstate = to_dpu_plane_state(drm_state); - - pstate->multirect_index = DPU_SSPP_RECT_SOLO; - pstate->multirect_mode = DPU_SSPP_MULTIRECT_NONE; -} - -int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane) -{ - struct dpu_plane_state *pstate[R_MAX]; - const struct drm_plane_state *drm_state[R_MAX]; - struct dpu_rect src[R_MAX], dst[R_MAX]; - struct dpu_plane *dpu_plane[R_MAX]; - const struct dpu_format *fmt[R_MAX]; - bool q16_data = true; - int i, buffer_lines; - unsigned int max_tile_height = 1; - bool parallel_fetch_qualified = true; - bool has_tiled_rect = false; - - for (i = 0; i < R_MAX; i++) { - const struct msm_format *msm_fmt; - - drm_state[i] = i ? plane->r1 : plane->r0; - msm_fmt = msm_framebuffer_format(drm_state[i]->fb); - fmt[i] = to_dpu_format(msm_fmt); - - if (DPU_FORMAT_IS_UBWC(fmt[i])) { - has_tiled_rect = true; - if (fmt[i]->tile_height > max_tile_height) - max_tile_height = fmt[i]->tile_height; - } - } - - for (i = 0; i < R_MAX; i++) { - int width_threshold; - - pstate[i] = to_dpu_plane_state(drm_state[i]); - dpu_plane[i] = to_dpu_plane(drm_state[i]->plane); - - if (pstate[i] == NULL) { - DPU_ERROR("DPU plane state of plane id %d is NULL\n", - drm_state[i]->plane->base.id); - return -EINVAL; - } - - POPULATE_RECT(&src[i], drm_state[i]->src_x, drm_state[i]->src_y, - drm_state[i]->src_w, drm_state[i]->src_h, q16_data); - POPULATE_RECT(&dst[i], drm_state[i]->crtc_x, - drm_state[i]->crtc_y, drm_state[i]->crtc_w, - drm_state[i]->crtc_h, !q16_data); - - if (src[i].w != dst[i].w || src[i].h != dst[i].h) { - DPU_ERROR_PLANE(dpu_plane[i], - "scaling is not supported in multirect mode\n"); - return -EINVAL; - } - - if (DPU_FORMAT_IS_YUV(fmt[i])) { - DPU_ERROR_PLANE(dpu_plane[i], - "Unsupported format for multirect mode\n"); - return -EINVAL; - } - - /** - * SSPP PD_MEM is split half - one for each RECT. - * Tiled formats need 5 lines of buffering while fetching - * whereas linear formats need only 2 lines. - * So we cannot support more than half of the supported SSPP - * width for tiled formats. - */ - width_threshold = dpu_plane[i]->pipe_sblk->common->maxlinewidth; - if (has_tiled_rect) - width_threshold /= 2; - - if (parallel_fetch_qualified && src[i].w > width_threshold) - parallel_fetch_qualified = false; - - } - - /* Validate RECT's and set the mode */ - - /* Prefer PARALLEL FETCH Mode over TIME_MX Mode */ - if (parallel_fetch_qualified) { - pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; - pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_PARALLEL; - - goto done; - } - - /* TIME_MX Mode */ - buffer_lines = 2 * max_tile_height; - - if ((dst[R1].y >= dst[R0].y + dst[R0].h + buffer_lines) || - (dst[R0].y >= dst[R1].y + dst[R1].h + buffer_lines)) { - pstate[R0]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX; - pstate[R1]->multirect_mode = DPU_SSPP_MULTIRECT_TIME_MX; - } else { - DPU_ERROR( - "No multirect mode possible for the planes (%d - %d)\n", - drm_state[R0]->plane->base.id, - drm_state[R1]->plane->base.id); - return -EINVAL; - } - -done: - if (dpu_plane[R0]->is_virtual) { - pstate[R0]->multirect_index = DPU_SSPP_RECT_1; - pstate[R1]->multirect_index = DPU_SSPP_RECT_0; - } else { - pstate[R0]->multirect_index = DPU_SSPP_RECT_0; - pstate[R1]->multirect_index = DPU_SSPP_RECT_1; - }; - - DPU_DEBUG_PLANE(dpu_plane[R0], "R0: %d - %d\n", - pstate[R0]->multirect_mode, pstate[R0]->multirect_index); - DPU_DEBUG_PLANE(dpu_plane[R1], "R1: %d - %d\n", - pstate[R1]->multirect_mode, pstate[R1]->multirect_index); - return 0; -} - /** * dpu_plane_get_ctl_flush - get control flush for the given plane * @plane: Pointer to drm plane structure @@ -1329,38 +1172,23 @@ static int dpu_plane_sspp_atomic_update(struct drm_plane *plane, if (pdpu->pipe_hw->ops.setup_rects) { pdpu->pipe_hw->ops.setup_rects(pdpu->pipe_hw, - &pdpu->pipe_cfg, - pstate->multirect_index); + &pdpu->pipe_cfg); } - if (pdpu->pipe_hw->ops.setup_pe && - (pstate->multirect_index != DPU_SSPP_RECT_1)) + if (pdpu->pipe_hw->ops.setup_pe) pdpu->pipe_hw->ops.setup_pe(pdpu->pipe_hw, &pstate->pixel_ext); - /** - * when programmed in multirect mode, scalar block will be - * bypassed. Still we need to update alpha and bitwidth - * ONLY for RECT0 - */ - if (pdpu->pipe_hw->ops.setup_scaler && - pstate->multirect_index != DPU_SSPP_RECT_1) + if (pdpu->pipe_hw->ops.setup_scaler) pdpu->pipe_hw->ops.setup_scaler(pdpu->pipe_hw, &pdpu->pipe_cfg, &pstate->pixel_ext, &pstate->scaler3_cfg); - if (pdpu->pipe_hw->ops.setup_multirect) - pdpu->pipe_hw->ops.setup_multirect( - pdpu->pipe_hw, - pstate->multirect_index, - pstate->multirect_mode); - if (pdpu->pipe_hw->ops.setup_format) { src_flags = 0x0; /* update format */ - pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, fmt, src_flags, - pstate->multirect_index); + pdpu->pipe_hw->ops.setup_format(pdpu->pipe_hw, fmt, src_flags); if (pdpu->pipe_hw->ops.setup_cdp) { struct dpu_hw_pipe_cdp_cfg *cdp_cfg = &pstate->cdp_cfg; @@ -1398,44 +1226,12 @@ static int dpu_plane_sspp_atomic_update(struct drm_plane *plane, return 0; } -static void _dpu_plane_atomic_disable(struct drm_plane *plane, - struct drm_plane_state *old_state) -{ - struct dpu_plane *pdpu; - struct drm_plane_state *state; - struct dpu_plane_state *pstate; - - if (!plane) { - DPU_ERROR("invalid plane\n"); - return; - } else if (!plane->state) { - DPU_ERROR("invalid plane state\n"); - return; - } else if (!old_state) { - DPU_ERROR("invalid old state\n"); - return; - } - - pdpu = to_dpu_plane(plane); - state = plane->state; - pstate = to_dpu_plane_state(state); - - DPU_EVT32(DRMID(plane), is_dpu_plane_virtual(plane), - pstate->multirect_mode); - - pstate->pending = true; - - if (is_dpu_plane_virtual(plane) && - pdpu->pipe_hw && pdpu->pipe_hw->ops.setup_multirect) - pdpu->pipe_hw->ops.setup_multirect(pdpu->pipe_hw, - DPU_SSPP_RECT_SOLO, DPU_SSPP_MULTIRECT_NONE); -} - static void dpu_plane_atomic_update(struct drm_plane *plane, struct drm_plane_state *old_state) { struct dpu_plane *pdpu; struct drm_plane_state *state; + struct dpu_plane_state *pstate; if (!plane) { DPU_ERROR("invalid plane\n"); @@ -1448,11 +1244,12 @@ static void dpu_plane_atomic_update(struct drm_plane *plane, pdpu = to_dpu_plane(plane); pdpu->is_error = false; state = plane->state; + pstate = to_dpu_plane_state(state); DPU_DEBUG_PLANE(pdpu, "\n"); if (!dpu_plane_sspp_enabled(state)) { - _dpu_plane_atomic_disable(plane, old_state); + pstate->pending = true; } else { int ret; @@ -1830,18 +1627,12 @@ enum dpu_sspp dpu_plane_pipe(struct drm_plane *plane) return plane ? to_dpu_plane(plane)->pipe : SSPP_NONE; } -bool is_dpu_plane_virtual(struct drm_plane *plane) -{ - return plane ? to_dpu_plane(plane)->is_virtual : false; -} - /* initialize plane */ struct drm_plane *dpu_plane_init(struct drm_device *dev, uint32_t pipe, bool primary_plane, - unsigned long possible_crtcs, u32 master_plane_id) + unsigned long possible_crtcs) { - struct drm_plane *plane = NULL, *master_plane = NULL; - const struct dpu_format_extended *format_list; + struct drm_plane *plane = NULL; struct dpu_plane *pdpu; struct msm_drm_private *priv; struct dpu_kms *kms; @@ -1882,18 +1673,10 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, /* cache local stuff for later */ plane = &pdpu->base; pdpu->pipe = pipe; - pdpu->is_virtual = (master_plane_id != 0); - INIT_LIST_HEAD(&pdpu->mplane_list); - master_plane = drm_plane_find(dev, NULL, master_plane_id); - if (master_plane) { - struct dpu_plane *mpdpu = to_dpu_plane(master_plane); - - list_add_tail(&pdpu->mplane_list, &mpdpu->mplane_list); - } /* initialize underlying h/w driver */ - pdpu->pipe_hw = dpu_hw_sspp_init(pipe, kms->mmio, kms->catalog, - master_plane_id != 0); + pdpu->pipe_hw = dpu_hw_sspp_init(pipe, kms->mmio, kms->catalog); + if (IS_ERR(pdpu->pipe_hw)) { DPU_ERROR("[%u]SSPP init failed\n", pipe); ret = PTR_ERR(pdpu->pipe_hw); @@ -1911,12 +1694,8 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, goto clean_sspp; } - if (!master_plane_id) - format_list = pdpu->pipe_sblk->format_list; - else - format_list = pdpu->pipe_sblk->virt_format_list; - - pdpu->nformats = dpu_populate_formats(format_list, + pdpu->nformats = dpu_populate_formats( + pdpu->pipe_sblk->format_list, pdpu->formats, 0, ARRAY_SIZE(pdpu->formats)); @@ -1959,8 +1738,8 @@ struct drm_plane *dpu_plane_init(struct drm_device *dev, mutex_init(&pdpu->lock); - DPU_DEBUG("%s created for pipe:%u id:%u virtual:%u\n", pdpu->pipe_name, - pipe, plane->base.id, master_plane_id); + DPU_DEBUG("%s created for pipe:%u id:%u\n", pdpu->pipe_name, + pipe, plane->base.id); return plane; clean_sspp: diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h index f6fe6dd..3795a336 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.h @@ -46,8 +46,6 @@ struct dpu_plane_state { struct msm_gem_address_space *aspace; void *input_fence; enum dpu_stage stage; - uint32_t multirect_index; - uint32_t multirect_mode; bool pending; /* scaler configuration */ @@ -57,16 +55,6 @@ struct dpu_plane_state { struct dpu_hw_pipe_cdp_cfg cdp_cfg; }; -/** - * struct dpu_multirect_plane_states: Defines multirect pair of drm plane states - * @r0: drm plane configured on rect 0 - * @r1: drm plane configured on rect 1 - */ -struct dpu_multirect_plane_states { - const struct drm_plane_state *r0; - const struct drm_plane_state *r1; -}; - #define to_dpu_plane_state(x) \ container_of(x, struct dpu_plane_state, base) @@ -78,14 +66,6 @@ struct dpu_multirect_plane_states { enum dpu_sspp dpu_plane_pipe(struct drm_plane *plane); /** - * is_dpu_plane_virtual - check for virtual plane - * @plane: Pointer to DRM plane object - * returns: true - if the plane is virtual - * false - if the plane is primary - */ -bool is_dpu_plane_virtual(struct drm_plane *plane); - -/** * dpu_plane_get_ctl_flush - get control flush mask * @plane: Pointer to DRM plane object * @ctl: Pointer to control hardware @@ -124,27 +104,11 @@ void dpu_plane_get_ctl_flush(struct drm_plane *plane, struct dpu_hw_ctl *ctl, * @pipe: dpu hardware pipe identifier * @primary_plane: true if this pipe is primary plane for crtc * @possible_crtcs: bitmask of crtc that can be attached to the given pipe - * @master_plane_id: primary plane id of a multirect pipe. 0 value passed for - * a regular plane initialization. A non-zero primary plane - * id will be passed for a virtual pipe initialization. * */ struct drm_plane *dpu_plane_init(struct drm_device *dev, uint32_t pipe, bool primary_plane, - unsigned long possible_crtcs, u32 master_plane_id); - -/** - * dpu_plane_validate_multirecti_v2 - validate the multirect planes - * against hw limitations - * @plane: drm plate states of the multirect pair - */ -int dpu_plane_validate_multirect_v2(struct dpu_multirect_plane_states *plane); - -/** - * dpu_plane_clear_multirect - clear multirect bits for the given pipe - * @drm_state: Pointer to DRM plane state - */ -void dpu_plane_clear_multirect(const struct drm_plane_state *drm_state); + unsigned long possible_crtcs); /** * dpu_plane_wait_input_fence - wait for input fence object diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h index 1affc7f..3958994 100644 --- a/drivers/gpu/drm/msm/msm_drv.h +++ b/drivers/gpu/drm/msm/msm_drv.h @@ -62,7 +62,7 @@ #define NUM_DOMAINS 4 /* one for KMS, then one per gpu core (?) */ #define MAX_CRTCS 8 -#define MAX_PLANES 20 +#define MAX_PLANES 12 #define MAX_ENCODERS 8 #define MAX_BRIDGES 8 #define MAX_CONNECTORS 8