From patchwork Mon Sep 24 11:36:21 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Patchwork-Submitter: Yannick FERTRE X-Patchwork-Id: 10612307 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 6B137913 for ; Mon, 24 Sep 2018 12:05:27 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 5882C29569 for ; Mon, 24 Sep 2018 12:05:27 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 4BDCD2960A; Mon, 24 Sep 2018 12:05:27 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id BBEB129569 for ; Mon, 24 Sep 2018 12:05:26 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id ADC596E208; Mon, 24 Sep 2018 12:05:25 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org X-Greylist: delayed 1718 seconds by postgrey-1.36 at gabe; Mon, 24 Sep 2018 12:05:24 UTC Received: from mx07-00178001.pphosted.com (mx08-00178001.pphosted.com [91.207.212.93]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2DAE06E208 for ; Mon, 24 Sep 2018 12:05:24 +0000 (UTC) Received: from pps.filterd (m0046660.ppops.net [127.0.0.1]) by mx08-.pphosted.com (8.16.0.21/8.16.0.21) with SMTP id w8OBXbjm011901; Mon, 24 Sep 2018 13:36:40 +0200 Received: from beta.dmz-eu.st.com (beta.dmz-eu.st.com [164.129.1.35]) by mx08-00178001.pphosted.com with ESMTP id 2mnav5arvx-1 (version=TLSv1 cipher=ECDHE-RSA-AES256-SHA bits=256 verify=NOT); Mon, 24 Sep 2018 13:36:40 +0200 Received: from zeta.dmz-eu.st.com (zeta.dmz-eu.st.com [164.129.230.9]) by beta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 3E3E83D; Mon, 24 Sep 2018 11:36:40 +0000 (GMT) Received: from Webmail-eu.st.com (Safex1hubcas23.st.com [10.75.90.46]) by zeta.dmz-eu.st.com (STMicroelectronics) with ESMTP id 1EE545650; Mon, 24 Sep 2018 11:36:40 +0000 (GMT) Received: from SAFEX1HUBCAS21.st.com (10.75.90.44) by SAFEX1HUBCAS23.st.com (10.75.90.46) with Microsoft SMTP Server (TLS) id 14.3.361.1; Mon, 24 Sep 2018 13:36:39 +0200 Received: from localhost (10.201.23.97) by Webmail-ga.st.com (10.75.90.48) with Microsoft SMTP Server (TLS) id 14.3.361.1; Mon, 24 Sep 2018 13:36:39 +0200 From: =?utf-8?q?Yannick_Fertr=C3=A9?= To: Yannick Fertre , Philippe Cornu , Benjamin Gaignard , Vincent Abriou , Gustavo Padovan , Maarten Lankhorst , Sean Paul , David Airlie , , Subject: [PATCH v1 2/2] drm/stm: ltdc: Solve issue on pixel clock & data enable polarity Date: Mon, 24 Sep 2018 13:36:21 +0200 Message-ID: <1537788981-21479-3-git-send-email-yannick.fertre@st.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1537788981-21479-1-git-send-email-yannick.fertre@st.com> References: <1537788981-21479-1-git-send-email-yannick.fertre@st.com> MIME-Version: 1.0 X-Originating-IP: [10.201.23.97] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10434:, , definitions=2018-09-24_07:, , signatures=0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Wrong flags used for set the pixel clock & data enable polarities. Add trace for polarities of hsync, vsync, data enabled & pixel clock. Signed-off-by: Yannick Fertré Reviewed-by: Benjamin Gaignard --- drivers/gpu/drm/stm/ltdc.c | 23 +++++++++++++++++++---- 1 file changed, 19 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/stm/ltdc.c b/drivers/gpu/drm/stm/ltdc.c index 808d9fb..f671abc 100644 --- a/drivers/gpu/drm/stm/ltdc.c +++ b/drivers/gpu/drm/stm/ltdc.c @@ -517,7 +517,7 @@ static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc) struct videomode vm; u32 hsync, vsync, accum_hbp, accum_vbp, accum_act_w, accum_act_h; u32 total_width, total_height; - u32 val; + u32 val = 0; drm_display_mode_to_videomode(mode, &vm); @@ -538,7 +538,22 @@ static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc) total_height = accum_act_h + vm.vfront_porch; /* Configures the HS, VS, DE and PC polarities. Default Active Low */ - val = 0; + if (vm.flags & DISPLAY_FLAGS_HSYNC_LOW) + DRM_DEBUG_DRIVER("Horizontal Synchronization polarity is active low"); + if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH) + DRM_DEBUG_DRIVER("Horizontal Synchronization polarity is active high"); + if (vm.flags & DISPLAY_FLAGS_VSYNC_LOW) + DRM_DEBUG_DRIVER("Vertical Synchronization polarity is active low"); + if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH) + DRM_DEBUG_DRIVER("Vertical Synchronization polarity is active high"); + if (vm.flags & DISPLAY_FLAGS_DE_LOW) + DRM_DEBUG_DRIVER("Data Enable polarity is active low"); + if (vm.flags & DISPLAY_FLAGS_DE_HIGH) + DRM_DEBUG_DRIVER("Data Enable polarity is active high"); + if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) + DRM_DEBUG_DRIVER("Pixel clock polarity is active low"); + if (vm.flags & DISPLAY_FLAGS_PIXDATA_POSEDGE) + DRM_DEBUG_DRIVER("Pixel clock polarity is active high"); if (vm.flags & DISPLAY_FLAGS_HSYNC_HIGH) val |= GCR_HSPOL; @@ -546,10 +561,10 @@ static void ltdc_crtc_mode_set_nofb(struct drm_crtc *crtc) if (vm.flags & DISPLAY_FLAGS_VSYNC_HIGH) val |= GCR_VSPOL; - if (vm.flags & DISPLAY_FLAGS_DE_HIGH) + if (vm.flags & DISPLAY_FLAGS_DE_LOW) val |= GCR_DEPOL; - if (vm.flags & DISPLAY_FLAGS_PIXDATA_NEGEDGE) + if (vm.flags & DISPLAY_FLAGS_PIXDATA_POSEDGE) val |= GCR_PCPOL; reg_update_bits(ldev->regs, LTDC_GCR,