diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index dd17528..5d501c8 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -166,7 +166,6 @@ enum dpu_enc_rc_states {
  * @delayed_off_work:		delayed worker to schedule disabling of
  *				clks and resources after IDLE_TIMEOUT time.
  * @vsync_event_work:		worker to handle vsync event for autorefresh
- * @topology:                   topology of the display
  * @idle_timeout:		idle timeout duration in milliseconds
  */
 struct dpu_encoder_virt {
@@ -202,7 +201,6 @@ struct dpu_encoder_virt {
 	enum dpu_enc_rc_states rc_state;
 	struct kthread_delayed_work delayed_off_work;
 	struct kthread_work vsync_event_work;
-	struct msm_display_topology topology;
 
 	u32 idle_timeout;
 };
@@ -557,25 +555,19 @@ static void _dpu_encoder_adjust_mode(struct drm_connector *connector,
 	}
 }
 
-static struct msm_display_topology dpu_encoder_get_topology(
+static void _dpu_encoder_get_topology(
 			struct dpu_encoder_virt *dpu_enc,
-			struct dpu_kms *dpu_kms,
+			struct drm_crtc_state *crtc_state,
 			struct drm_display_mode *mode)
 {
-	struct msm_display_topology topology;
-	int i, intf_count = 0;
-
-	for (i = 0; i < MAX_PHYS_ENCODERS_PER_VIRTUAL; i++)
-		if (dpu_enc->phys_encs[i])
-			intf_count++;
+	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
 
 	/* User split topology for width > 1080 */
-	topology.num_lm = (mode->vdisplay > MAX_VDISPLAY_SPLIT) ? 2 : 1;
-	topology.num_enc = 0;
-	topology.num_intf = intf_count;
-
-	return topology;
+	dpu_cstate->num_mixers = (mode->vdisplay > MAX_VDISPLAY_SPLIT) ? 2 : 1;
+	dpu_cstate->num_ctls = dpu_enc->num_phys_encs;
+	dpu_cstate->num_intfs = dpu_enc->num_phys_encs;
 }
+
 static int dpu_encoder_virt_atomic_check(
 		struct drm_encoder *drm_enc,
 		struct drm_crtc_state *crtc_state,
@@ -586,7 +578,6 @@ static int dpu_encoder_virt_atomic_check(
 	struct dpu_kms *dpu_kms;
 	const struct drm_display_mode *mode;
 	struct drm_display_mode *adj_mode;
-	struct msm_display_topology topology;
 	int i = 0;
 	int ret = 0;
 
@@ -632,11 +623,9 @@ static int dpu_encoder_virt_atomic_check(
 		}
 	}
 
-	topology = dpu_encoder_get_topology(dpu_enc, dpu_kms, adj_mode);
-
+	_dpu_encoder_get_topology(dpu_enc, crtc_state, adj_mode);
 	if (!ret && drm_atomic_crtc_needs_modeset(crtc_state))
-		ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, crtc_state,
-				     topology);
+		ret = dpu_rm_reserve(&dpu_kms->rm, drm_enc, crtc_state);
 
 	if (!ret)
 		drm_mode_set_crtcinfo(adj_mode, 0);
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
index bb59250..85a0fe2 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.c
@@ -23,11 +23,9 @@
 
 /**
  * struct dpu_rm_requirements - Reservation requirements parameter bundle
- * @topology:  selected topology for the display
  * @hw_res:	   Hardware resources required as reported by the encoders
  */
 struct dpu_rm_requirements {
-	struct msm_display_topology topology;
 	struct dpu_encoder_hw_resources hw_res;
 };
 
@@ -231,9 +229,9 @@ int dpu_rm_init(struct dpu_rm *rm,
 	return rc;
 }
 
-static bool _dpu_rm_needs_split_display(const struct msm_display_topology *top)
+static bool _dpu_rm_needs_split_display(const struct dpu_crtc_state *dpu_cstate)
 {
-	return top->num_intf > 1;
+	return dpu_cstate->num_intfs > 1;
 }
 
 /**
@@ -241,7 +239,6 @@ static bool _dpu_rm_needs_split_display(const struct msm_display_topology *top)
  *	proposed use case requirements, incl. hardwired dependent blocks like
  *	pingpong
  * @rm: dpu resource manager handle
- * @reqs: proposed use case requirements
  * @lm: proposed layer mixer, function checks if lm, and all other hardwired
  *      blocks connected to the lm (pp) is available and appropriate
  * @pp: output parameter, pingpong block attached to the layer mixer.
@@ -252,7 +249,6 @@ static bool _dpu_rm_needs_split_display(const struct msm_display_topology *top)
  */
 static bool _dpu_rm_check_lm_and_get_connected_blks(
 		struct dpu_rm *rm,
-		struct dpu_rm_requirements *reqs,
 		struct dpu_rm_hw_blk *lm,
 		struct dpu_rm_hw_blk **pp,
 		struct dpu_rm_hw_blk *primary_lm)
@@ -297,9 +293,7 @@ static bool _dpu_rm_check_lm_and_get_connected_blks(
 }
 
 static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
-			       struct dpu_crtc_state *dpu_cstate,
-			       struct dpu_rm_requirements *reqs)
-
+			       struct dpu_crtc_state *dpu_cstate)
 {
 	struct dpu_rm_hw_blk *lm[MAX_BLOCKS];
 	struct dpu_rm_hw_blk *pp[MAX_BLOCKS];
@@ -308,17 +302,12 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
 	int lm_count = 0;
 	int i, rc = 0;
 
-	if (!reqs->topology.num_lm) {
-		DPU_ERROR("invalid number of lm: %d\n", reqs->topology.num_lm);
-		return -EINVAL;
-	}
-
 	/* Find a primary mixer */
 	list_for_each_entry(iter_i, blk_list, list) {
 		if (iter_i->in_use)
 			continue;
 
-		if (lm_count == reqs->topology.num_lm)
+		if (lm_count == dpu_cstate->num_mixers)
 			break;
 
 		memset(&lm, 0, sizeof(lm));
@@ -328,8 +317,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
 		lm[lm_count] = iter_i;
 
 		if (!_dpu_rm_check_lm_and_get_connected_blks(
-				rm, reqs, lm[lm_count],
-				&pp[lm_count], NULL))
+				rm, lm[lm_count], &pp[lm_count], NULL))
 			continue;
 
 		++lm_count;
@@ -339,15 +327,14 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
 			if (iter_j->in_use)
 				continue;
 
-			if (lm_count == reqs->topology.num_lm)
+			if (lm_count == dpu_cstate->num_mixers)
 				break;
 
 			if (iter_i == iter_j)
 				continue;
 
 			if (!_dpu_rm_check_lm_and_get_connected_blks(
-					rm, reqs, iter_j,
-					&pp[lm_count], iter_i))
+					rm, iter_j, &pp[lm_count], iter_i))
 				continue;
 
 			lm[lm_count] = iter_j;
@@ -355,7 +342,7 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
 		}
 	}
 
-	if (lm_count != reqs->topology.num_lm) {
+	if (lm_count != dpu_cstate->num_mixers) {
 		DPU_DEBUG("unable to find appropriate mixers\n");
 		return -ENAVAIL;
 	}
@@ -374,29 +361,22 @@ static int _dpu_rm_reserve_lms(struct dpu_rm *rm,
 					 pp[i]->hw->id);
 	}
 
-	dpu_cstate->num_mixers = lm_count;
-
 	return rc;
 }
 
 static int _dpu_rm_reserve_ctls(
 		struct dpu_rm *rm,
-		struct dpu_crtc_state *dpu_cstate,
-		const struct msm_display_topology *top)
+		struct dpu_crtc_state *dpu_cstate)
 {
 	struct dpu_rm_hw_blk *ctls[MAX_BLOCKS];
 	struct dpu_rm_hw_blk *iter;
 	struct list_head *blk_list = &rm->hw_blks[DPU_HW_BLK_CTL];
-
-	int i = 0, num_ctls = 0;
+	int i = 0;
 	bool needs_split_display = false;
 
 	memset(&ctls, 0, sizeof(ctls));
 
-	/* each hw_intf needs its own hw_ctrl to program its control path */
-	num_ctls = top->num_intf;
-
-	needs_split_display = _dpu_rm_needs_split_display(top);
+	needs_split_display = _dpu_rm_needs_split_display(dpu_cstate);
 
 	list_for_each_entry(iter, blk_list, list)  {
 		const struct dpu_hw_ctl *ctl = to_dpu_hw_ctl(iter->hw);
@@ -416,22 +396,20 @@ static int _dpu_rm_reserve_ctls(
 		ctls[i] = iter;
 		DPU_DEBUG("ctl %d match\n", iter->hw->id);
 
-		if (++i == num_ctls)
+		if (++i == dpu_cstate->num_ctls)
 			break;
 	}
 
-	if (i != num_ctls)
+	if (i != dpu_cstate->num_ctls)
 		return -ENAVAIL;
 
-	for (i = 0; i < ARRAY_SIZE(ctls) && i < num_ctls; i++) {
+	for (i = 0; i < ARRAY_SIZE(ctls) && i < dpu_cstate->num_ctls; i++) {
 		ctls[i]->in_use = true;
 		dpu_cstate->hw_ctls[i] = to_dpu_hw_ctl(ctls[i]->hw);
 
 		trace_dpu_rm_reserve_ctls(ctls[i]->hw->id, DPU_HW_BLK_CTL);
 	}
 
-	dpu_cstate->num_ctls = num_ctls;
-
 	return 0;
 }
 
@@ -470,7 +448,8 @@ static int _dpu_rm_reserve_intfs(
 		trace_dpu_rm_reserve_intf(intf_blk->hw->id, DPU_HW_BLK_INTF);
 	}
 
-	dpu_cstate->num_intfs = num_intfs;
+	if (dpu_cstate->num_intfs != num_intfs)
+		return -EINVAL;
 
 	return 0;
 }
@@ -482,13 +461,13 @@ static int _dpu_rm_make_reservation(
 {
 	int ret;
 
-	ret = _dpu_rm_reserve_lms(rm, dpu_cstate, reqs);
+	ret = _dpu_rm_reserve_lms(rm, dpu_cstate);
 	if (ret) {
 		DPU_ERROR("unable to find appropriate mixers\n");
 		return ret;
 	}
 
-	ret = _dpu_rm_reserve_ctls(rm, dpu_cstate, &reqs->topology);
+	ret = _dpu_rm_reserve_ctls(rm, dpu_cstate);
 	if (ret) {
 		DPU_ERROR("unable to find appropriate CTL\n");
 		return ret;
@@ -503,21 +482,11 @@ static int _dpu_rm_make_reservation(
 	return ret;
 }
 
-static int _dpu_rm_populate_requirements(
-		struct dpu_rm *rm,
+static void _dpu_rm_populate_requirements(
 		struct drm_encoder *enc,
-		struct dpu_rm_requirements *reqs,
-		struct msm_display_topology req_topology)
+		struct dpu_rm_requirements *reqs)
 {
 	dpu_encoder_get_hw_resources(enc, &reqs->hw_res);
-
-	reqs->topology = req_topology;
-
-	DRM_DEBUG_KMS("num_lm: %d num_enc: %d num_intf: %d\n",
-		      reqs->topology.num_lm, reqs->topology.num_enc,
-		      reqs->topology.num_intf);
-
-	return 0;
 }
 
 static int _dpu_rm_release_hw(struct dpu_rm *rm, enum dpu_hw_blk_type type,
@@ -591,8 +560,7 @@ void dpu_rm_release(struct dpu_rm *rm, struct drm_crtc_state *crtc_state)
 int dpu_rm_reserve(
 		struct dpu_rm *rm,
 		struct drm_encoder *enc,
-		struct drm_crtc_state *crtc_state,
-		struct msm_display_topology topology)
+		struct drm_crtc_state *crtc_state)
 {
 	struct dpu_rm_requirements reqs;
 	struct dpu_crtc_state *dpu_cstate = to_dpu_crtc_state(crtc_state);
@@ -607,18 +575,14 @@ int dpu_rm_reserve(
 
 	mutex_lock(&rm->rm_lock);
 
-	ret = _dpu_rm_populate_requirements(rm, enc, &reqs, topology);
-	if (ret) {
-		DPU_ERROR("failed to populate hw requirements\n");
-		goto end;
-	}
+	_dpu_rm_populate_requirements(enc, &reqs);
 
 	ret = _dpu_rm_make_reservation(rm, dpu_cstate, &reqs);
 	if (ret) {
 		DPU_ERROR("failed to reserve hw resources: %d\n", ret);
 		_dpu_rm_release_reservation(rm, dpu_cstate);
 	}
-end:
+
 	mutex_unlock(&rm->rm_lock);
 
 	return ret;
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
index 415eeec..1626cef 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_rm.h
@@ -62,13 +62,11 @@ int dpu_rm_init(struct dpu_rm *rm,
  * @rm: DPU Resource Manager handle
  * @drm_enc: DRM Encoder handle
  * @crtc_state: Proposed Atomic DRM CRTC State handle
- * @topology: Pointer to topology info for the display
  * @Return: 0 on Success otherwise -ERROR
  */
 int dpu_rm_reserve(struct dpu_rm *rm,
 		struct drm_encoder *drm_enc,
-		struct drm_crtc_state *crtc_state,
-		struct msm_display_topology topology);
+		struct drm_crtc_state *crtc_state);
 
 /**
  * dpu_rm_release - Given the encoder for the display chain, release any
diff --git a/drivers/gpu/drm/msm/msm_drv.h b/drivers/gpu/drm/msm/msm_drv.h
index 9d11f32..3515fb0 100644
--- a/drivers/gpu/drm/msm/msm_drv.h
+++ b/drivers/gpu/drm/msm/msm_drv.h
@@ -113,18 +113,6 @@ enum msm_event_wait {
 };
 
 /**
- * struct msm_display_topology - defines a display topology pipeline
- * @num_lm:       number of layer mixers used
- * @num_enc:      number of compression encoder blocks used
- * @num_intf:     number of interfaces the panel is mounted on
- */
-struct msm_display_topology {
-	u32 num_lm;
-	u32 num_enc;
-	u32 num_intf;
-};
-
-/**
  * struct msm_display_info - defines display properties
  * @intf_type:          DRM_MODE_CONNECTOR_ display type
  * @capabilities:       Bitmask of display flags
