| Message ID | 1539278337-15037-1-git-send-email-abhinavk@codeaurora.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v2] drm/msm/dsi: fix dsi clock names in DSI 10nm PLL driver | expand |
On Thu, Oct 11, 2018, 1:19 PM Abhinav Kumar <abhinavk@codeaurora.org> wrote: > Fix the dsi clock names in the DSI 10nm PLL driver to > match the names in the dispcc driver as those are > according to the clock plan of the chipset. > > Changes in v2: > - Update the clock diagram with the new clock name > > Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org> > Reviewed-by: Sean Paul <seanpaul@chromium.org> (On mobile, apologies for html email) --- > drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 8 ++++---- > 1 file changed, 4 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c > b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c > index 41bec57..3120562 100644 > --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c > +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c > @@ -17,7 +17,7 @@ > * | | > * | | > * +---------+ | +----------+ | +----+ > - * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0pllbyte > + * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- > dsi0_phy_pll_out_byteclk > * +---------+ | +----------+ | +----+ > * | | > * | | > dsi0_pll_by_2_bit_clk > @@ -25,7 +25,7 @@ > * | | +----+ | |\ > dsi0_pclk_mux > * | |--| /2 |--o--| \ | > * | | +----+ | \ | > +---------+ > - * | --------------| |--o--| > div_7_4 |-- dsi0pll > + * | --------------| |--o--| > div_7_4 |-- dsi0_phy_pll_out_dsiclk > * |------------------------------| / > +---------+ > * | +-----+ | / > * -----------| /4? |--o----------|/ > @@ -690,7 +690,7 @@ static int pll_10nm_register(struct dsi_pll_10nm > *pll_10nm) > > hws[num++] = hw; > > - snprintf(clk_name, 32, "dsi%dpllbyte", pll_10nm->id); > + snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_10nm->id); > snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id); > > /* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */ > @@ -739,7 +739,7 @@ static int pll_10nm_register(struct dsi_pll_10nm > *pll_10nm) > > hws[num++] = hw; > > - snprintf(clk_name, 32, "dsi%dpll", pll_10nm->id); > + snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_10nm->id); > snprintf(parent, 32, "dsi%d_pclk_mux", pll_10nm->id); > > /* PIX CLK DIV : DIV_CTRL_7_4*/ > -- > The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, > a Linux Foundation Collaborative Project > > <div dir="auto"><div><br><br><div class="gmail_quote"><div dir="ltr">On Thu, Oct 11, 2018, 1:19 PM Abhinav Kumar <<a href="mailto:abhinavk@codeaurora.org">abhinavk@codeaurora.org</a>> wrote:<br></div><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex">Fix the dsi clock names in the DSI 10nm PLL driver to<br> match the names in the dispcc driver as those are<br> according to the clock plan of the chipset.<br> <br> Changes in v2:<br> - Update the clock diagram with the new clock name<br> <br> Signed-off-by: Abhinav Kumar <<a href="mailto:abhinavk@codeaurora.org" target="_blank" rel="noreferrer">abhinavk@codeaurora.org</a>><br></blockquote></div></div><div dir="auto"><br></div><div dir="auto">Reviewed-by: Sean Paul <<a href="mailto:seanpaul@chromium.org">seanpaul@chromium.org</a>></div><div dir="auto"><br></div><div dir="auto">(On mobile, apologies for html email)</div><div dir="auto"><br></div><div dir="auto"><div class="gmail_quote"><blockquote class="gmail_quote" style="margin:0 0 0 .8ex;border-left:1px #ccc solid;padding-left:1ex"> ---<br> drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 8 ++++----<br> 1 file changed, 4 insertions(+), 4 deletions(-)<br> <br> diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c<br> index 41bec57..3120562 100644<br> --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c<br> +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c<br> @@ -17,7 +17,7 @@<br> * | |<br> * | |<br> * +---------+ | +----------+ | +----+<br> - * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0pllbyte<br> + * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk<br> * +---------+ | +----------+ | +----+<br> * | |<br> * | | dsi0_pll_by_2_bit_clk<br> @@ -25,7 +25,7 @@<br> * | | +----+ | |\ dsi0_pclk_mux<br> * | |--| /2 |--o--| \ |<br> * | | +----+ | \ | +---------+<br> - * | --------------| |--o--| div_7_4 |-- dsi0pll<br> + * | --------------| |--o--| div_7_4 |-- dsi0_phy_pll_out_dsiclk<br> * |------------------------------| / +---------+<br> * | +-----+ | /<br> * -----------| /4? |--o----------|/<br> @@ -690,7 +690,7 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm)<br> <br> hws[num++] = hw;<br> <br> - snprintf(clk_name, 32, "dsi%dpllbyte", pll_10nm->id);<br> + snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_10nm->id);<br> snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id);<br> <br> /* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */<br> @@ -739,7 +739,7 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm)<br> <br> hws[num++] = hw;<br> <br> - snprintf(clk_name, 32, "dsi%dpll", pll_10nm->id);<br> + snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_10nm->id);<br> snprintf(parent, 32, "dsi%d_pclk_mux", pll_10nm->id);<br> <br> /* PIX CLK DIV : DIV_CTRL_7_4*/<br> -- <br> The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,<br> a Linux Foundation Collaborative Project<br> <br> </blockquote></div></div></div>
diff --git a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c index 41bec57..3120562 100644 --- a/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c +++ b/drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c @@ -17,7 +17,7 @@ * | | * | | * +---------+ | +----------+ | +----+ - * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0pllbyte + * dsi0vco_clk ---| out_div |--o--| divl_3_0 |--o--| /8 |-- dsi0_phy_pll_out_byteclk * +---------+ | +----------+ | +----+ * | | * | | dsi0_pll_by_2_bit_clk @@ -25,7 +25,7 @@ * | | +----+ | |\ dsi0_pclk_mux * | |--| /2 |--o--| \ | * | | +----+ | \ | +---------+ - * | --------------| |--o--| div_7_4 |-- dsi0pll + * | --------------| |--o--| div_7_4 |-- dsi0_phy_pll_out_dsiclk * |------------------------------| / +---------+ * | +-----+ | / * -----------| /4? |--o----------|/ @@ -690,7 +690,7 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm) hws[num++] = hw; - snprintf(clk_name, 32, "dsi%dpllbyte", pll_10nm->id); + snprintf(clk_name, 32, "dsi%d_phy_pll_out_byteclk", pll_10nm->id); snprintf(parent, 32, "dsi%d_pll_bit_clk", pll_10nm->id); /* DSI Byte clock = VCO_CLK / OUT_DIV / BIT_DIV / 8 */ @@ -739,7 +739,7 @@ static int pll_10nm_register(struct dsi_pll_10nm *pll_10nm) hws[num++] = hw; - snprintf(clk_name, 32, "dsi%dpll", pll_10nm->id); + snprintf(clk_name, 32, "dsi%d_phy_pll_out_dsiclk", pll_10nm->id); snprintf(parent, 32, "dsi%d_pclk_mux", pll_10nm->id); /* PIX CLK DIV : DIV_CTRL_7_4*/
Fix the dsi clock names in the DSI 10nm PLL driver to match the names in the dispcc driver as those are according to the clock plan of the chipset. Changes in v2: - Update the clock diagram with the new clock name Signed-off-by: Abhinav Kumar <abhinavk@codeaurora.org> --- drivers/gpu/drm/msm/dsi/pll/dsi_pll_10nm.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)