| Message ID | 1545638931-24938-16-git-send-email-yongqiang.niu@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | add drm support for MT8183 | expand |
Hi, Yongqiang: On Mon, 2018-12-24 at 16:08 +0800, Yongqiang Niu wrote: > This patch add RDMA1 fifo size into RDMA private data > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 16 +++++++++++++++- > 1 file changed, 15 insertions(+), 1 deletion(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > index b0a5cff..3f9b4d4 100644 > --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c > @@ -53,12 +53,14 @@ > #define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16) > #define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16) > #define RDMA_FIFO_SIZE(rdma) ((rdma)->data->fifo_size) > +#define RDMA_FIFO_SIZE1(rdma) ((rdma)->data->fifo_size1) > #define DISP_RDMA_MEM_START_ADDR 0x0f00 > > #define RDMA_MEM_GMC 0x40402020 > > struct mtk_disp_rdma_data { > unsigned int fifo_size; > + unsigned int fifo_size1; > }; > > /** > @@ -137,11 +139,17 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, > { > unsigned int threshold; > unsigned int reg; > + unsigned int rdma_fifo_size; > struct mtk_disp_rdma *rdma = comp_to_rdma(comp); > > rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff, width); > rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff, height); > > + if (comp->id == DDP_COMPONENT_RDMA1) > + rdma_fifo_size = RDMA_FIFO_SIZE1(rdma); > + else > + rdma_fifo_size = RDMA_FIFO_SIZE(rdma); > + It looks like that mt81830-rdma0 and mt8183-rdma1 are different in hardware, so I think fifo_size should be decided by something from device tree rather than from its name. Maybe add a property 'FIFO_SIZE' in rdma device node or create an additional compatible string for mt8183-rdma1. Regards, CK > /* > * Enable FIFO underflow since DSI and DPI can't be blocked. > * Keep the FIFO pseudo size reset default of 8 KiB. Set the > @@ -149,8 +157,12 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, > * account for blanking, and with a pixel depth of 4 bytes: > */ > threshold = width * height * vrefresh * 4 * 7 / 1000000; > + > + if (threshold > rdma_fifo_size) > + threshold = rdma_fifo_size; > + > reg = RDMA_FIFO_UNDERFLOW_EN | > - RDMA_FIFO_PSEUDO_SIZE(RDMA_FIFO_SIZE(rdma)) | > + RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) | > RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); > writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON); > } > @@ -330,10 +342,12 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev) > > static const struct mtk_disp_rdma_data mt2701_rdma_driver_data = { > .fifo_size = SZ_4K, > + .fifo_size1 = SZ_4K, > }; > > static const struct mtk_disp_rdma_data mt8173_rdma_driver_data = { > .fifo_size = SZ_8K, > + .fifo_size1 = SZ_8K, > }; > > static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index b0a5cff..3f9b4d4 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -53,12 +53,14 @@ #define RDMA_FIFO_PSEUDO_SIZE(bytes) (((bytes) / 16) << 16) #define RDMA_OUTPUT_VALID_FIFO_THRESHOLD(bytes) ((bytes) / 16) #define RDMA_FIFO_SIZE(rdma) ((rdma)->data->fifo_size) +#define RDMA_FIFO_SIZE1(rdma) ((rdma)->data->fifo_size1) #define DISP_RDMA_MEM_START_ADDR 0x0f00 #define RDMA_MEM_GMC 0x40402020 struct mtk_disp_rdma_data { unsigned int fifo_size; + unsigned int fifo_size1; }; /** @@ -137,11 +139,17 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, { unsigned int threshold; unsigned int reg; + unsigned int rdma_fifo_size; struct mtk_disp_rdma *rdma = comp_to_rdma(comp); rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_0, 0xfff, width); rdma_update_bits(comp, DISP_REG_RDMA_SIZE_CON_1, 0xfffff, height); + if (comp->id == DDP_COMPONENT_RDMA1) + rdma_fifo_size = RDMA_FIFO_SIZE1(rdma); + else + rdma_fifo_size = RDMA_FIFO_SIZE(rdma); + /* * Enable FIFO underflow since DSI and DPI can't be blocked. * Keep the FIFO pseudo size reset default of 8 KiB. Set the @@ -149,8 +157,12 @@ static void mtk_rdma_config(struct mtk_ddp_comp *comp, unsigned int width, * account for blanking, and with a pixel depth of 4 bytes: */ threshold = width * height * vrefresh * 4 * 7 / 1000000; + + if (threshold > rdma_fifo_size) + threshold = rdma_fifo_size; + reg = RDMA_FIFO_UNDERFLOW_EN | - RDMA_FIFO_PSEUDO_SIZE(RDMA_FIFO_SIZE(rdma)) | + RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) | RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold); writel(reg, comp->regs + DISP_REG_RDMA_FIFO_CON); } @@ -330,10 +342,12 @@ static int mtk_disp_rdma_remove(struct platform_device *pdev) static const struct mtk_disp_rdma_data mt2701_rdma_driver_data = { .fifo_size = SZ_4K, + .fifo_size1 = SZ_4K, }; static const struct mtk_disp_rdma_data mt8173_rdma_driver_data = { .fifo_size = SZ_8K, + .fifo_size1 = SZ_8K, }; static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
This patch add RDMA1 fifo size into RDMA private data Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-)