diff --git a/tests/amdgpu/basic_tests.c b/tests/amdgpu/basic_tests.c
index dbae4d5..d4b0faf 100644
--- a/tests/amdgpu/basic_tests.c
+++ b/tests/amdgpu/basic_tests.c
@@ -49,6 +49,7 @@ static void amdgpu_userptr_test(void);
 static void amdgpu_semaphore_test(void);
 static void amdgpu_sync_dependency_test(void);
 static void amdgpu_bo_eviction_test(void);
+static void amdgpu_dispatch_test(void);
 
 static void amdgpu_command_submission_write_linear_helper(unsigned ip_type);
 static void amdgpu_command_submission_const_fill_helper(unsigned ip_type);
@@ -70,6 +71,7 @@ CU_TestInfo basic_tests[] = {
 	{ "Command submission Test (SDMA)", amdgpu_command_submission_sdma },
 	{ "SW semaphore Test",  amdgpu_semaphore_test },
 	{ "Sync dependency Test",  amdgpu_sync_dependency_test },
+	{ "Dispatch Test",  amdgpu_dispatch_test },
 	CU_TEST_INFO_NULL,
 };
 #define BUFFER_SIZE (8 * 1024)
@@ -117,6 +119,7 @@ CU_TestInfo basic_tests[] = {
 #define PACKET3(op, n)	((PACKET_TYPE3 << 30) |				\
 			 (((op) & 0xFF) << 8) |				\
 			 ((n) & 0x3FFF) << 16)
+#define PACKET3_COMPUTE(op, n) PACKET3(op, n) | (1 << 1)
 
 /* Packet 3 types */
 #define	PACKET3_NOP					0x10
@@ -245,8 +248,8 @@ CU_TestInfo basic_tests[] = {
 #define		PACKET3_SET_SH_REG_START			0x00002c00
 
 #define	PACKET3_DISPATCH_DIRECT				0x15
-
-
+#define PACKET3_EVENT_WRITE				0x46
+#define PACKET3_ACQUIRE_MEM				0x58
 /* gfx 8 */
 #define mmCOMPUTE_PGM_LO                                                        0x2e0c
 #define mmCOMPUTE_PGM_RSRC1                                                     0x2e12
@@ -286,6 +289,21 @@ static  uint32_t shader_bin[] = {
 #define CODE_OFFSET 512
 #define DATA_OFFSET 1024
 
+static const uint32_t bufferclear_cs_shader_gfx9[] = {
+    0xD1FD0000, 0x04010C08, 0x7E020204, 0x7E040205,
+    0x7E060206, 0x7E080207, 0xE01C2000, 0x80000100,
+    0xBF810000
+};
+
+static const uint32_t bufferclear_cs_shader_registers_gfx9[][2] = {
+	{0x2E12, 0x000C0041},	//{ mmCOMPUTE_PGM_RSRC1,	  0x000C0041 },
+	{0x2E13, 0x00000090},	//{ mmCOMPUTE_PGM_RSRC2,	  0x00000090 },
+	{0x2E07, 0x00000040},	//{ mmCOMPUTE_NUM_THREAD_X, 0x00000040 },
+	{0x2E08, 0x00000001},	//{ mmCOMPUTE_NUM_THREAD_Y, 0x00000001 },
+	{0x2E09, 0x00000001},	//{ mmCOMPUTE_NUM_THREAD_Z, 0x00000001 }
+};
+
+static const uint32_t bufferclear_cs_shader_registers_num_gfx9 = 5;
 
 int amdgpu_bo_alloc_and_map_raw(amdgpu_device_handle dev, unsigned size,
 			unsigned alignment, unsigned heap, uint64_t alloc_flags,
@@ -1883,3 +1901,196 @@ static void amdgpu_sync_dependency_test(void)
 
 	free(ibs_request.dependencies);
 }
+
+static int amdgpu_dispatch_init(uint32_t ip_type,
+					uint32_t version,
+					uint32_t *ptr)
+{
+	int i = 0;
+
+	/* Write context control and load shadowing register if necessary */
+	if (ip_type == AMDGPU_HW_IP_GFX) {
+		ptr[i++] = PACKET3(PKT3_CONTEXT_CONTROL, 1);
+		ptr[i++] = 0x80000000;
+		ptr[i++] = 0x80000000;
+	}
+
+	/* Issue commands to set default compute state. */
+	/* clear mmCOMPUTE_START_Z - mmCOMPUTE_START_X */
+	ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 3);
+	ptr[i++] = 0x204;
+	i += 3;
+	/* clear mmCOMPUTE_RESOURCE_LIMITS */
+	ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
+	ptr[i++] = 0x215;
+	ptr[i++] = 0;
+	/* clear mmCOMPUTE_TMPRING_SIZE */
+	ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
+	ptr[i++] = 0x218;
+	ptr[i++] = 0;
+
+	return i;
+}
+
+static int amdgpu_dispatch_write_cumask(uint32_t ip_type,
+					uint32_t version,
+					uint32_t *ptr)
+{
+	int i = 0;
+
+	/*  Issue commands to set cu mask used in current dispatch */
+	/* set mmCOMPUTE_STATIC_THREAD_MGMT_SE1 - mmCOMPUTE_STATIC_THREAD_MGMT_SE0 */
+	ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 2);
+	ptr[i++] = 0x216;
+	ptr[i++] = 0xffffffff;
+	ptr[i++] = 0xffffffff;
+	/* set mmCOMPUTE_STATIC_THREAD_MGMT_SE3 - mmCOMPUTE_STATIC_THREAD_MGMT_SE2 */
+	ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 2);
+	ptr[i++] = 0x219;
+	ptr[i++] = 0xffffffff;
+	ptr[i++] = 0xffffffff;
+
+	return i;
+}
+
+static int amdgpu_dispatch_write2hw(uint32_t ip_type,
+					uint32_t version,
+					uint32_t *ptr,
+					uint64_t shader_addr)
+{
+	int i, j;
+
+	i = 0;
+
+	/* Writes shader state to HW */
+	/* set mmCOMPUTE_PGM_HI - mmCOMPUTE_PGM_LO */
+	ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 2);
+	ptr[i++] = 0x20c;
+	ptr[i++] = (shader_addr >> 8);
+	ptr[i++] = (shader_addr >> 40);
+	/* write sh regs*/
+	for (j = 0; j < bufferclear_cs_shader_registers_num_gfx9; j++) {
+		ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 1);
+		/* - Gfx9ShRegBase */
+		ptr[i++] = bufferclear_cs_shader_registers_gfx9[j][0] - 0x2c00;
+		ptr[i++] = bufferclear_cs_shader_registers_gfx9[j][1];
+	}
+
+	return i;
+}
+
+static void amdgpu_memset_dispatch_test(uint32_t ip_type)
+{
+	amdgpu_context_handle context_handle;
+	amdgpu_bo_handle bo_dst, bo_shader, resources[2];
+	volatile unsigned char *ptr_dst;
+	void *ptr_shader;
+	uint64_t mc_address_dst, mc_address_shader;
+	amdgpu_va_handle va_dst, va_shader;
+	int i, j, r;
+	uint32_t *ptr;
+	int bo_dst_size = 16384;
+	int bo_shader_size = 4096;
+	struct amdgpu_cs_request ibs_request = {0};
+	struct amdgpu_cs_ib_info ib_info= {0};
+	uint32_t version, ring_id;
+	struct drm_amdgpu_info_hw_ip info;
+
+	r = amdgpu_query_hw_ip_info(device_handle, ip_type, 0, &info);
+	CU_ASSERT_EQUAL(r, 0);
+
+	version = info.hw_ip_version_major;
+	if (version != 9) {
+		printf("\tSkip...memset dispatch test is only supported with gfx9\n");
+		return;
+	}
+
+	ptr = calloc(256, sizeof(*ptr));
+	CU_ASSERT_NOT_EQUAL(ptr, NULL);
+
+	r = amdgpu_cs_ctx_create(device_handle, &context_handle);
+	CU_ASSERT_EQUAL(r, 0);
+
+	r = amdgpu_bo_alloc_and_map(device_handle, bo_shader_size, 4096,
+					AMDGPU_GEM_DOMAIN_VRAM, 0,
+					&bo_shader, &ptr_shader,
+					&mc_address_shader, &va_shader);
+	CU_ASSERT_EQUAL(r, 0);
+
+	memcpy(ptr_shader, bufferclear_cs_shader_gfx9, sizeof(bufferclear_cs_shader_gfx9));
+
+	for (ring_id = 0; (1 << ring_id) & info.available_rings; ring_id++) {
+		r = amdgpu_bo_alloc_and_map(device_handle, bo_dst_size, 4096,
+						AMDGPU_GEM_DOMAIN_VRAM, 0,
+						&bo_dst, &ptr_dst,
+						&mc_address_dst, &va_dst);
+		CU_ASSERT_EQUAL(r, 0);
+
+		i = 0;
+		i += amdgpu_dispatch_init(ip_type, version, ptr + i);
+
+		/*  Issue commands to set cu mask used in current dispatch */
+		i += amdgpu_dispatch_write_cumask(ip_type, version, ptr + i);
+
+		/* Writes shader state to HW */
+		i += amdgpu_dispatch_write2hw(ip_type, version, ptr + i, mc_address_shader);
+
+		/* Write constant data */
+		/* Writes the UAV constant data to the SGPRs. */
+		ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 4);
+		ptr[i++] = 0x240;
+		ptr[i++] = mc_address_dst;
+		ptr[i++] = (mc_address_dst > 32) | 0x100000;
+		ptr[i++] = 0x400;
+		ptr[i++] = 0x74fac;
+
+		/* Sets a range of pixel shader constants */
+		ptr[i++] = PACKET3_COMPUTE(PKT3_SET_SH_REG, 4);
+		ptr[i++] = 0x244;
+		ptr[i++] = 0x22222222;
+		ptr[i++] = 0x22222222;
+		ptr[i++] = 0x22222222;
+		ptr[i++] = 0x22222222;
+
+		/* dispatch direct command */
+		ptr[i++] = PACKET3_COMPUTE(PACKET3_DISPATCH_DIRECT, 3);
+		ptr[i++] = 0x10;
+		ptr[i++] = 1;
+		ptr[i++] = 1;
+		ptr[i++] = 1;
+
+		while (i & 7)
+			ptr[i++] =  0xffff1000; /* type3 nop packet */
+
+		resources[0] = bo_dst;
+		resources[1] = bo_shader;
+		amdgpu_test_exec_cs_helper(context_handle,
+					   ip_type, ring_id,
+					   i, ptr,
+					   2, resources,
+					   &ib_info, &ibs_request);
+
+		/* verify if memset test result meets with expected */
+		i = 0;
+		while(i < bo_dst_size) {
+			CU_ASSERT_EQUAL(ptr_dst[i++], 0x22);
+		}
+
+		r = amdgpu_bo_unmap_and_free(bo_dst, va_dst, mc_address_dst, bo_dst_size);
+		CU_ASSERT_EQUAL(r, 0);
+	}
+
+	free(ptr);
+
+	r = amdgpu_bo_unmap_and_free(bo_shader, va_shader, mc_address_shader, bo_shader_size);
+	CU_ASSERT_EQUAL(r, 0);
+	r = amdgpu_cs_ctx_free(context_handle);
+	CU_ASSERT_EQUAL(r, 0);
+}
+
+static void amdgpu_dispatch_test(void)
+{
+	amdgpu_memset_dispatch_test(AMDGPU_HW_IP_GFX);
+
+	amdgpu_memset_dispatch_test(AMDGPU_HW_IP_COMPUTE);
+}
