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[86.31.179.135]) by smtp.gmail.com with ESMTPSA id s10sm4583941wrv.56.2019.03.18.12.40.56 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Mon, 18 Mar 2019 12:40:56 -0700 (PDT) From: Peter Griffin To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, mark.rutland@arm.com, p.zabel@pengutronix.de, xuwei5@hisilicon.com, mturquette@baylibre.com, sboyd@kernel.org Subject: [PATCH v1 3/6] arm64: dts: hisilicon: Add Mali-450 MP4 GPU DT entry Date: Mon, 18 Mar 2019 19:38:48 +0000 Message-Id: <1552937931-23050-4-git-send-email-peter.griffin@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1552937931-23050-1-git-send-email-peter.griffin@linaro.org> References: <1552937931-23050-1-git-send-email-peter.griffin@linaro.org> X-Mailman-Approved-At: Tue, 19 Mar 2019 08:12:25 +0000 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=iYcbdw0SobNZ1DKEtyOsg/AhnPu/CmThFhgWWs7DOwA=; b=Zave381f6F6eYXUT5XE8kYOOwujnnpASeD67mm7RFLbGbsjITUf2fUwDUipX5c2jSj OdBWKis4xAPiNst8Ut6f2EcApUFinBFLLvGPFIek6CrwuelpHoRJH6duE1Dfo7TJhHm2 CJOqQcxCdoFUrwYGKNQrH/vbpe/xWMNezLEF4kSfh3W/iDg9dhwnlpdlW1X75ZGOEr7m w3E95sEwUSUYTj09Y8A5xGWJIBnxdEIF7/Y66RxxUyimmX44WKgcxB2ew1LndlqGWUnP 7H/WiI+WTpwDcLdDE+1vABKwGIMnoAMpMrPxqu1gP1/9qD/x/XtFwjcwoWdDHMNSKs6e H37g== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, yuq825@gmail.com MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP hi6220 has a Mali450 MP4 so lets add it into the DT. Signed-off-by: Peter Griffin --- arch/arm64/boot/dts/hisilicon/hi6220.dtsi | 38 +++++++++++++++++++++++++++++++ 1 file changed, 38 insertions(+) diff --git a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi index 108e2a4..2072b63 100644 --- a/arch/arm64/boot/dts/hisilicon/hi6220.dtsi +++ b/arch/arm64/boot/dts/hisilicon/hi6220.dtsi @@ -260,6 +260,7 @@ compatible = "hisilicon,hi6220-aoctrl", "syscon"; reg = <0x0 0xf7800000 0x0 0x2000>; #clock-cells = <1>; + #reset-cells = <1>; }; sys_ctrl: sys_ctrl@f7030000 { @@ -1021,6 +1022,43 @@ clock-names = "apb_pclk"; cpu = <&cpu7>; }; + + mali: gpu@f4080000 { + compatible = "hisilicon,hi6220-mali", "arm,mali-450"; + reg = <0x0 0xf4080000 0x0 0x00040000>; + interrupt-parent = <&gic>; + interrupts = , + , + , + , + , + , + , + , + , + , + ; + + interrupt-names = "gp", + "gpmmu", + "pp", + "pp0", + "ppmmu0", + "pp1", + "ppmmu1", + "pp2", + "ppmmu2", + "pp3", + "ppmmu3"; + clocks = <&media_ctrl HI6220_G3D_CLK>, + <&media_ctrl HI6220_G3D_PCLK>; + clock-names = "core", "bus"; + assigned-clocks = <&media_ctrl HI6220_G3D_CLK>, + <&media_ctrl HI6220_G3D_PCLK>; + assigned-clock-rates = <500000000>, <144000000>; + reset-names = "ao_g3d", "media_g3d"; + resets = <&ao_ctrl AO_G3D>, <&media_ctrl MEDIA_G3D>; + }; }; };