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[86.31.179.135]) by smtp.gmail.com with ESMTPSA id t76sm5700147wmt.8.2019.04.19.01.35.03 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Fri, 19 Apr 2019 01:35:03 -0700 (PDT) From: Peter Griffin To: linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, john.stultz@linaro.org, airlied@linux.ie, daniel@ffwll.ch, robh+dt@kernel.org, mark.rutland@arm.com, p.zabel@pengutronix.de, xuwei5@hisilicon.com, mturquette@baylibre.com, sboyd@kernel.org, yuq825@gmail.com Subject: [PATCH v2 1/6] dt-bindings: gpu: mali-utgard: add hisilicon, hi6220-mali compatible Date: Fri, 19 Apr 2019 09:32:56 +0100 Message-Id: <1555662781-22570-2-git-send-email-peter.griffin@linaro.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1555662781-22570-1-git-send-email-peter.griffin@linaro.org> References: <1555662781-22570-1-git-send-email-peter.griffin@linaro.org> X-Mailman-Approved-At: Sat, 20 Apr 2019 08:47:32 +0000 X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=linaro.org; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=MCTEvmabwYzI3ci+NujQrB/hypflAW8OQ75e8/ggXfk=; b=MmDEdzRcl9DaSM0D19sHLRP9UUgUb3DU9U/mKJ4uV0lViP+8Df/cara5+dwmvId2vi WCLQOT1S9LX6lveDGKTjokIESoUs5zV+Yvi2kw6zAVVXQxJinyhsP81cBiz3+fbe0KXq ib3QilCDqnukXnjqqNJxDG7lbKiTmelD2kCgZCXW6E3bamJvWp+dJHAKTUt9EIDg5PJO AsDxgXHM9sRx+3nZAzUT1J9faizEapC+cpYUkDdC4uGnPeBtXmOu2wab7KpbQzOGQDRM YwN/fvrXryGp/kH7lktMqf7IosiwgS0IQxI/hbqoi3Y+bV/6gjxR+f9ffx6d6suPdsih gDBw== X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, linux-clk@vger.kernel.org, dri-devel@lists.freedesktop.org, lima@lists.freedesktop.org MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP The Hisilicon hi6220 uses a Mali-450MP4 with 4 PPs, so add a compatible for it. Signed-off-by: Peter Griffin Reviewed-by: Rob Herring --- Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt index 3f128e4..2a16b0c 100644 --- a/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt +++ b/Documentation/devicetree/bindings/gpu/arm,mali-utgard.txt @@ -21,6 +21,7 @@ Required properties: + rockchip,rk3228-mali + rockchip,rk3328-mali + stericsson,db8500-mali + + hisilicon,hi6220-mali - reg: Physical base address and length of the GPU registers @@ -91,6 +92,10 @@ to specify one more vendor-specific compatible, among: * interrupt-names and interrupts: + combined: combined interrupt of all of the above lines + - hisilicon,hi6220-mali + Required properties: + * resets: phandles to the reset lines for the GPU + Example: mali: gpu@1c40000 {