From patchwork Tue May 21 16:14:01 2019 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jordan Crouse X-Patchwork-Id: 10954285 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id A53EF76 for ; Tue, 21 May 2019 16:15:03 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 954E92898C for ; Tue, 21 May 2019 16:15:03 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 89BB428AB9; Tue, 21 May 2019 16:15:03 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00,MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 173A628AB3 for ; Tue, 21 May 2019 16:15:03 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id AAE99893D5; Tue, 21 May 2019 16:15:01 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from smtp.codeaurora.org (smtp.codeaurora.org [198.145.29.96]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2075F893D5; Tue, 21 May 2019 16:15:01 +0000 (UTC) Received: by smtp.codeaurora.org (Postfix, from userid 1000) id 9466861B2F; Tue, 21 May 2019 16:14:34 +0000 (UTC) Received: from jcrouse1-lnx.qualcomm.com (i-global254.qualcomm.com [199.106.103.254]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-SHA256 (128/128 bits)) (No client certificate requested) (Authenticated sender: jcrouse@smtp.codeaurora.org) by smtp.codeaurora.org (Postfix) with ESMTPSA id B1A0961A86; Tue, 21 May 2019 16:14:28 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 smtp.codeaurora.org B1A0961A86 From: Jordan Crouse To: freedreno@lists.freedesktop.org Subject: [PATCH v2 13/15] drm/msm: Add support for IOMMU auxiliary domains Date: Tue, 21 May 2019 10:14:01 -0600 Message-Id: <1558455243-32746-14-git-send-email-jcrouse@codeaurora.org> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1558455243-32746-1-git-send-email-jcrouse@codeaurora.org> References: <1558455243-32746-1-git-send-email-jcrouse@codeaurora.org> X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1558455300; bh=wBZB+LFIv8r0uTFu6MNzs2A3S+65mKQ9oZ1KI8mimLg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=A3CmxoVGlCvSBnw7hDy9bcfHUIKvPUcaeb79+FChNdQXdIas96imdKsy7RW0guG66 r5Ce0PVISNaz3kz7BYKeMJoblBrbbsdbpoEu9NuQeFEQwMA4urmPvPG+V8T/WkOPni g01xMWfta/1SgbrIMsYFpsFH22DOLMm7idBVHH7Q= X-Mailman-Original-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=codeaurora.org; s=default; t=1558455269; bh=wBZB+LFIv8r0uTFu6MNzs2A3S+65mKQ9oZ1KI8mimLg=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=Ek7yM0JTN7/EroFyqpNnwY+9yO09i01GBdDvXdsoRObaxi723hceSPWLOpHNhW90G sEGFubvEg2b0OX8da5+gnHGWnS2oPmnO5ZNHJUxNLjvxd6aF/KRB5n1vqNPa3aBY0Q 0sNpQi/FUSSBCuPsIOCwkTu0DCN2+v5GB1+aeHPg= X-Mailman-Original-Authentication-Results: pdx-caf-mail.web.codeaurora.org; dmarc=none (p=none dis=none) header.from=codeaurora.org X-Mailman-Original-Authentication-Results: pdx-caf-mail.web.codeaurora.org; spf=none smtp.mailfrom=jcrouse@codeaurora.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: jean-philippe.brucker@arm.com, linux-arm-msm@vger.kernel.org, dianders@chromium.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, David Airlie , hoegsberg@google.com, Sean Paul MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Add support for creating a auxiliary domain from the IOMMU device to implement per-instance pagetables. Also add a helper function to return the pagetable base address (ttbr) and asid to the caller so that the GPU target code can set up the pagetable switch. Signed-off-by: Jordan Crouse --- drivers/gpu/drm/msm/msm_iommu.c | 97 +++++++++++++++++++++++++++++++++++++++++ drivers/gpu/drm/msm/msm_mmu.h | 4 ++ 2 files changed, 101 insertions(+) diff --git a/drivers/gpu/drm/msm/msm_iommu.c b/drivers/gpu/drm/msm/msm_iommu.c index 1926329..adf9f18 100644 --- a/drivers/gpu/drm/msm/msm_iommu.c +++ b/drivers/gpu/drm/msm/msm_iommu.c @@ -21,9 +21,21 @@ struct msm_iommu { struct msm_mmu base; struct iommu_domain *domain; + u64 ttbr; + u32 asid; }; #define to_msm_iommu(x) container_of(x, struct msm_iommu, base) +/* + * The asid is currently unused for arm-smmu-v2 since all the pagetable + * switching does a TLBIALL but still assign a somewhat unique number per + * instance to leave open the possibility of being smarter about it + * + * Accepted range is 32 to 255 (starting at 32 gives a cushion for the asids + * assigned to the real context banks in the arm-smmu driver. + */ +static int msm_iommu_asid = 32; + static int msm_fault_handler(struct iommu_domain *domain, struct device *dev, unsigned long iova, int flags, void *arg) { @@ -34,6 +46,47 @@ static int msm_fault_handler(struct iommu_domain *domain, struct device *dev, return 0; } +static int msm_iommu_aux_attach(struct msm_mmu *mmu, const char * const *names, + int cnt) +{ + struct msm_iommu *iommu = to_msm_iommu(mmu); + int ret; + + /* Attach the aux device */ + ret = iommu_aux_attach_device(iommu->domain, mmu->dev); + if (ret) + return ret; + + /* Get the base address of the pagetable */ + ret = iommu_domain_get_attr(iommu->domain, DOMAIN_ATTR_PTBASE, + &iommu->ttbr); + if (ret) + return ret; + + /* + * Assign an asid for the instance even though the code doesn't + * currently support per-asid TLB invalidation. There isn't any + * protection on this so two instances could in theory end up with the + * same ASID but that would have very minor performance implications if + * per-ASID TLB invalidation were to be enabled in the future + */ + iommu->asid = msm_iommu_asid++; + + if (msm_iommu_asid > 0xff) + msm_iommu_asid = 32; + + return 0; +} + +static void msm_iommu_aux_detach(struct msm_mmu *mmu, const char * const *names, + int cnt) +{ + struct msm_iommu *iommu = to_msm_iommu(mmu); + + iommu->ttbr = 0; + iommu->asid = 0; +} + static int msm_iommu_attach(struct msm_mmu *mmu, const char * const *names, int cnt) { @@ -86,6 +139,50 @@ static const struct msm_mmu_funcs funcs = { .destroy = msm_iommu_destroy, }; +static const struct msm_mmu_funcs aux_funcs = { + .attach = msm_iommu_aux_attach, + .detach = msm_iommu_aux_detach, + .map = msm_iommu_map, + .unmap = msm_iommu_unmap, + .destroy = msm_iommu_destroy, +}; + +bool msm_iommu_get_ptinfo(struct msm_mmu *mmu, u64 *ttbr, u32 *asid) +{ + struct msm_iommu *iommu = to_msm_iommu(mmu); + + if (!iommu->ttbr) + return false; + + if (ttbr) + *ttbr = iommu->ttbr; + if (asid) + *asid = iommu->asid; + + return true; +} + + +struct msm_mmu *msm_iommu_new_instance(struct device *dev) +{ + struct msm_iommu *iommu; + + iommu = kzalloc(sizeof(*iommu), GFP_KERNEL); + if (!iommu) + return ERR_PTR(-ENOMEM); + + /* Create a new domain that will be attached as an aux domain */ + iommu->domain = iommu_domain_alloc(&platform_bus_type); + if (!iommu->domain) { + kfree(iommu); + return ERR_PTR(-ENOMEM); + } + + msm_mmu_init(&iommu->base, dev, &aux_funcs); + + return &iommu->base; +} + struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain) { struct msm_iommu *iommu; diff --git a/drivers/gpu/drm/msm/msm_mmu.h b/drivers/gpu/drm/msm/msm_mmu.h index d21b266..f430903 100644 --- a/drivers/gpu/drm/msm/msm_mmu.h +++ b/drivers/gpu/drm/msm/msm_mmu.h @@ -46,6 +46,10 @@ static inline void msm_mmu_init(struct msm_mmu *mmu, struct device *dev, struct msm_mmu *msm_iommu_new(struct device *dev, struct iommu_domain *domain); struct msm_mmu *msm_gpummu_new(struct device *dev, struct msm_gpu *gpu); +struct msm_mmu *msm_iommu_new_instance(struct device *dev); + +bool msm_iommu_get_ptinfo(struct msm_mmu *mmu, u64 *ttbr, u32 *asid); + static inline void msm_mmu_set_fault_handler(struct msm_mmu *mmu, void *arg, int (*handler)(void *arg, unsigned long iova, int flags)) {