| Message ID | 1562625253-29254-13-git-send-email-yongqiang.niu@mediatek.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | add drm support for MT8183 | expand |
Hi, Yongqiang: On Tue, 2019-07-09 at 06:33 +0800, yongqiang.niu@mediatek.com wrote: > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > Here is two modifition in this patch: > 1.bls->dpi0 and rdma1->dsi are differen usecase, > Split DISP_REG_CONFIG_DSI_SEL setting into anther usecase > 2.remove DISP_REG_CONFIG_DPI_SEL setting, DPI_SEL_IN_BLS is 0 and > this is same with hardware defautl setting, > You move 2 register setting out of the path from BLS to DPI0, does this path still work? Please make sure that all modification could work on all supported SoC. Regards, CK > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 3 +-- > 1 file changed, 1 insertion(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > index d015c1a..47b3e35 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > @@ -400,10 +400,9 @@ static void mtk_ddp_sout_sel(void __iomem *config_regs, > } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { > writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, > config_regs + DISP_REG_CONFIG_OUT_SEL); > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > writel_relaxed(DSI_SEL_IN_RDMA, > config_regs + DISP_REG_CONFIG_DSI_SEL); > - writel_relaxed(DPI_SEL_IN_BLS, > - config_regs + DISP_REG_CONFIG_DPI_SEL); > } > } >
On Wed, 2019-07-17 at 13:35 +0800, CK Hu wrote: > Hi, Yongqiang: > > On Tue, 2019-07-09 at 06:33 +0800, yongqiang.niu@mediatek.com wrote: > > From: Yongqiang Niu <yongqiang.niu@mediatek.com> > > > > Here is two modifition in this patch: > > 1.bls->dpi0 and rdma1->dsi are differen usecase, > > Split DISP_REG_CONFIG_DSI_SEL setting into anther usecase > > 2.remove DISP_REG_CONFIG_DPI_SEL setting, DPI_SEL_IN_BLS is 0 and > > this is same with hardware defautl setting, > > > > You move 2 register setting out of the path from BLS to DPI0, does this > path still work? Please make sure that all modification could work on > all supported SoC. > > Regards, > CK > DPI_SEL_IN_BLS is 0 and this is same with hardware default setting as description in patch. the removed sentence is useless. > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > > --- > > drivers/gpu/drm/mediatek/mtk_drm_ddp.c | 3 +-- > > 1 file changed, 1 insertion(+), 2 deletions(-) > > > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > index d015c1a..47b3e35 100644 > > --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c > > @@ -400,10 +400,9 @@ static void mtk_ddp_sout_sel(void __iomem *config_regs, > > } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { > > writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, > > config_regs + DISP_REG_CONFIG_OUT_SEL); > > + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { > > writel_relaxed(DSI_SEL_IN_RDMA, > > config_regs + DISP_REG_CONFIG_DSI_SEL); > > - writel_relaxed(DPI_SEL_IN_BLS, > > - config_regs + DISP_REG_CONFIG_DPI_SEL); > > } > > } > > > >
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c index d015c1a..47b3e35 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_ddp.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp.c @@ -400,10 +400,9 @@ static void mtk_ddp_sout_sel(void __iomem *config_regs, } else if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DPI0) { writel_relaxed(BLS_TO_DPI_RDMA1_TO_DSI, config_regs + DISP_REG_CONFIG_OUT_SEL); + } else if (cur == DDP_COMPONENT_RDMA1 && next == DDP_COMPONENT_DSI0) { writel_relaxed(DSI_SEL_IN_RDMA, config_regs + DISP_REG_CONFIG_DSI_SEL); - writel_relaxed(DPI_SEL_IN_BLS, - config_regs + DISP_REG_CONFIG_DPI_SEL); } }