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a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector2-amdcloud-onmicrosoft-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version:X-MS-Exchange-SenderADCheck; bh=jPXRsck+PnjbafITlvleuNArGe2odSSFtqN307AZ6/Y=; b=O0t6PM7UJ4MNmWhd7FqU3eC18yV/i6+yvzxQyDsPE1wB6pKjwZRjsIbx1e9VRnDQ7ohMPfAWNLBxpw62GvY3yLY2QoUBTP6z2q5pX2RugSrrjpZjqSzC/SrfTV8Cnh1e9zHxnReFV29ZUMWszIsqnXaDIMW95UTFWwV3b4Zb2xw= X-Mailman-Original-Authentication-Results: spf=none (sender IP is ) smtp.mailfrom=Ray.Huang@amd.com; X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "Tuikov, Luben" , "Koenig, Christian" , "Liu, Aaron" Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" From: Alex Deucher Add a flag to the GEM_CREATE ioctl to create encrypted buffers. Buffers with this flag set will be created with the TMZ bit set in the PTEs or engines accessing them. This is required in order to properly access the data from the engines. Signed-off-by: Alex Deucher Reviewed-by: Huang Rui --- include/uapi/drm/amdgpu_drm.h | 5 +++++ 1 file changed, 5 insertions(+) diff --git a/include/uapi/drm/amdgpu_drm.h b/include/uapi/drm/amdgpu_drm.h index f3ad429..f90b453 100644 --- a/include/uapi/drm/amdgpu_drm.h +++ b/include/uapi/drm/amdgpu_drm.h @@ -135,6 +135,11 @@ extern "C" { * releasing the memory */ #define AMDGPU_GEM_CREATE_VRAM_WIPE_ON_RELEASE (1 << 9) +/* Flag that BO will be encrypted and that the TMZ bit should be + * set in the PTEs when mapping this buffer via GPUVM or + * accessing it with various hw blocks + */ +#define AMDGPU_GEM_CREATE_ENCRYPTED (1 << 10) struct drm_amdgpu_gem_create_in { /** the requested memory size */