From patchwork Tue Jul 14 20:57:08 2020 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: "Chrisanthus, Anitha" X-Patchwork-Id: 11663655 Return-Path: Received: from mail.kernel.org (pdx-korg-mail-1.web.codeaurora.org [172.30.200.123]) by pdx-korg-patchwork-2.web.codeaurora.org (Postfix) with ESMTP id 3856560D for ; Tue, 14 Jul 2020 20:59:38 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 2069B2067D for ; Tue, 14 Jul 2020 20:59:38 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 2069B2067D Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=intel.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 6D6296E9CE; Tue, 14 Jul 2020 20:58:54 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mga09.intel.com (mga09.intel.com [134.134.136.24]) by gabe.freedesktop.org (Postfix) with ESMTPS id 0A9106E9B8; Tue, 14 Jul 2020 20:58:30 +0000 (UTC) IronPort-SDR: C/ITnAoHDzwixBxprsKEs9bNCDoCTItmTDk3TU/uyJNcW0ggaPY7lTVebL6GU5CtGTkkWfSMtk ZQKADe01WJSg== X-IronPort-AV: E=McAfee;i="6000,8403,9682"; a="150444568" X-IronPort-AV: E=Sophos;i="5.75,352,1589266800"; d="scan'208";a="150444568" X-Amp-Result: SKIPPED(no attachment in message) X-Amp-File-Uploaded: False Received: from orsmga008.jf.intel.com ([10.7.209.65]) by orsmga102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 14 Jul 2020 13:58:29 -0700 IronPort-SDR: lLplo203JGpv56biQ/rkrtuE4rdWmcRfDdRWvkYFXTnsd3Nzt41kGywf2UcSuZ12NfbgES5+o9 MNrz9FfTHcMg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.75,352,1589266800"; d="scan'208";a="316504146" Received: from ahanamuk-mobl.amr.corp.intel.com (HELO achrisan-DESK2.amr.corp.intel.com) ([10.251.155.61]) by orsmga008.jf.intel.com with ESMTP; 14 Jul 2020 13:58:29 -0700 From: Anitha Chrisanthus To: dri-devel@lists.freedesktop.org, anitha.chrisanthus@intel.com, bob.j.paauwe@intel.com, edmund.j.dea@intel.com Subject: [PATCH v2 22/59] drm/kmb: Set hardcoded values to LCD_VSYNC_START Date: Tue, 14 Jul 2020 13:57:08 -0700 Message-Id: <1594760265-11618-23-git-send-email-anitha.chrisanthus@intel.com> X-Mailer: git-send-email 2.7.4 In-Reply-To: <1594760265-11618-1-git-send-email-anitha.chrisanthus@intel.com> References: <1594760265-11618-1-git-send-email-anitha.chrisanthus@intel.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: daniel.vetter@intel.com, intel-gfx@lists.freedesktop.org, rodrigo.vivi@intel.com MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" Myriadx code has it set to these values. v2: upclassed dev_private Signed-off-by: Anitha Chrisanthus Reviewed-by: Bob Paauwe --- drivers/gpu/drm/kmb/kmb_crtc.c | 10 ++++++---- 1 file changed, 6 insertions(+), 4 deletions(-) diff --git a/drivers/gpu/drm/kmb/kmb_crtc.c b/drivers/gpu/drm/kmb/kmb_crtc.c index 5c1e858..eca0f3a 100644 --- a/drivers/gpu/drm/kmb/kmb_crtc.c +++ b/drivers/gpu/drm/kmb/kmb_crtc.c @@ -102,6 +102,9 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) kmb_write_lcd(dev_p, LCD_H_BACKPORCH, vm.hback_porch - 1); kmb_write_lcd(dev_p, LCD_H_FRONTPORCH, vm.hfront_porch - 1); kmb_write_lcd(dev_p, LCD_HSYNC_WIDTH, vm.hsync_len - 1); + /*this is hardcoded as 0 in the Myriadx code */ + kmb_write_lcd(dev_p, LCD_VSYNC_START, 0); + kmb_write_lcd(dev_p, LCD_VSYNC_END, 0); if (m->flags == DRM_MODE_FLAG_INTERLACE) { kmb_write_lcd(dev_p, @@ -112,10 +115,9 @@ static void kmb_crtc_mode_set_nofb(struct drm_crtc *crtc) LCD_V_FRONTPORCH_EVEN, vm.vfront_porch - 1); kmb_write_lcd(dev_p, LCD_V_ACTIVEHEIGHT_EVEN, m->crtc_vdisplay - 1); - kmb_write_lcd(dev_p, LCD_VSYNC_START_EVEN, - vsync_start_offset); - kmb_write_lcd(dev_p, LCD_VSYNC_END_EVEN, - vsync_end_offset); + /*this is hardcoded as 10 in the Myriadx code*/ + kmb_write_lcd(dev_p, LCD_VSYNC_START_EVEN, 10); + kmb_write_lcd(dev_p, LCD_VSYNC_END_EVEN, 10); } /* enable VL1 layer as default */ ctrl = LCD_CTRL_ENABLE | LCD_CTRL_VL1_ENABLE;