| Message ID | 1606298560-3003-1-git-send-email-kalyan_t@codeaurora.org (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v1] drm/msm/dpu: consider vertical front porch in the prefill bw calculation | expand |
On Wed, 25 Nov 2020 at 15:33, Kalyan Thota <kalyan_t@codeaurora.org> wrote: > > In case of panels with low vertical back porch, the prefill bw > requirement will be high as we will have less time(vbp+pw) to > fetch and fill the hw latency buffers before start of first line > in active period. > > For ex: > Say hw_latency_line_buffers = 24, and if blanking vbp+pw = 10 > Here we need to fetch 24 lines of data in 10 line times. > This will increase the bw to the ratio of linebuffers to blanking. > > DPU hw can also fetch data during vertical front porch provided > interface prefetch is enabled. Use vfp in the prefill calculation > as dpu driver enables prefetch if the blanking is not sufficient > to fill the latency lines. Tested on Xiaomi Poco F1 (sdm845). Tested-by: Amit Pundir <amit.pundir@linaro.org> > > Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org> > --- > drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 11 +++++++++-- > 1 file changed, 9 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > index 7ea90d2..315b999 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c > @@ -151,7 +151,7 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane, > u64 plane_bw; > u32 hw_latency_lines; > u64 scale_factor; > - int vbp, vpw; > + int vbp, vpw, vfp; > > pstate = to_dpu_plane_state(plane->state); > mode = &plane->state->crtc->mode; > @@ -164,6 +164,7 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane, > fps = drm_mode_vrefresh(mode); > vbp = mode->vtotal - mode->vsync_end; > vpw = mode->vsync_end - mode->vsync_start; > + vfp = mode->vsync_start - mode->vdisplay; > hw_latency_lines = dpu_kms->catalog->perf.min_prefill_lines; > scale_factor = src_height > dst_height ? > mult_frac(src_height, 1, dst_height) : 1; > @@ -176,7 +177,13 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane, > src_width * hw_latency_lines * fps * fmt->bpp * > scale_factor * mode->vtotal; > > - do_div(plane_prefill_bw, (vbp+vpw)); > + if ((vbp+vpw) > hw_latency_lines) > + do_div(plane_prefill_bw, (vbp+vpw)); > + else if ((vbp+vpw+vfp) < hw_latency_lines) > + do_div(plane_prefill_bw, (vbp+vpw+vfp)); > + else > + do_div(plane_prefill_bw, hw_latency_lines); > + > > pstate->plane_fetch_bw = max(plane_bw, plane_prefill_bw); > } > -- > 2.7.4 >
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c index 7ea90d2..315b999 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c +++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c @@ -151,7 +151,7 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane, u64 plane_bw; u32 hw_latency_lines; u64 scale_factor; - int vbp, vpw; + int vbp, vpw, vfp; pstate = to_dpu_plane_state(plane->state); mode = &plane->state->crtc->mode; @@ -164,6 +164,7 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane, fps = drm_mode_vrefresh(mode); vbp = mode->vtotal - mode->vsync_end; vpw = mode->vsync_end - mode->vsync_start; + vfp = mode->vsync_start - mode->vdisplay; hw_latency_lines = dpu_kms->catalog->perf.min_prefill_lines; scale_factor = src_height > dst_height ? mult_frac(src_height, 1, dst_height) : 1; @@ -176,7 +177,13 @@ static void _dpu_plane_calc_bw(struct drm_plane *plane, src_width * hw_latency_lines * fps * fmt->bpp * scale_factor * mode->vtotal; - do_div(plane_prefill_bw, (vbp+vpw)); + if ((vbp+vpw) > hw_latency_lines) + do_div(plane_prefill_bw, (vbp+vpw)); + else if ((vbp+vpw+vfp) < hw_latency_lines) + do_div(plane_prefill_bw, (vbp+vpw+vfp)); + else + do_div(plane_prefill_bw, hw_latency_lines); + pstate->plane_fetch_bw = max(plane_bw, plane_prefill_bw); }
In case of panels with low vertical back porch, the prefill bw requirement will be high as we will have less time(vbp+pw) to fetch and fill the hw latency buffers before start of first line in active period. For ex: Say hw_latency_line_buffers = 24, and if blanking vbp+pw = 10 Here we need to fetch 24 lines of data in 10 line times. This will increase the bw to the ratio of linebuffers to blanking. DPU hw can also fetch data during vertical front porch provided interface prefetch is enabled. Use vfp in the prefill calculation as dpu driver enables prefetch if the blanking is not sufficient to fill the latency lines. Signed-off-by: Kalyan Thota <kalyan_t@codeaurora.org> --- drivers/gpu/drm/msm/disp/dpu1/dpu_plane.c | 11 +++++++++-- 1 file changed, 9 insertions(+), 2 deletions(-)