diff mbox series

[v3,2/2] arm: dts: sc7180: Add support for gpu fuse

Message ID 1607337728-11398-2-git-send-email-akhilpo@codeaurora.org (mailing list archive)
State New, archived
Headers show
Series [v3,1/2] drm/msm: Add speed-bin support to a618 gpu | expand

Commit Message

Akhil P Oommen Dec. 7, 2020, 10:42 a.m. UTC 
Add support for gpu fuse to help identify the supported opps.

Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org>
---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

Comments

Akhil P Oommen Dec. 11, 2020, 11:55 a.m. UTC | #1 
On 12/7/2020 4:12 PM, Akhil P Oommen wrote:
> Add support for gpu fuse to help identify the supported opps.
> 
> Signed-off-by: Akhil P Oommen <akhilpo@codeaurora.org>
> ---
>   arch/arm64/boot/dts/qcom/sc7180.dtsi | 22 ++++++++++++++++++++++
>   1 file changed, 22 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> index 6678f1e..8cae3eb 100644
> --- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
> @@ -675,6 +675,11 @@
>   				reg = <0x25b 0x1>;
>   				bits = <1 3>;
>   			};
> +
> +			gpu_speed_bin: gpu_speed_bin@1d2 {
> +				reg = <0x1d2 0x2>;
> +				bits = <5 8>;
> +			};
>   		};
>   
>   		sdhc_1: sdhci@7c4000 {
> @@ -1907,52 +1912,69 @@
>   			operating-points-v2 = <&gpu_opp_table>;
>   			qcom,gmu = <&gmu>;
>   
> +			nvmem-cells = <&gpu_speed_bin>;
> +			nvmem-cell-names = "speed_bin";
> +
>   			interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
>   			interconnect-names = "gfx-mem";
>   
>   			gpu_opp_table: opp-table {
>   				compatible = "operating-points-v2";
>   
> +				opp-825000000 {
> +					opp-hz = /bits/ 64 <825000000>;
> +					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
> +					opp-peak-kBps = <8532000>;
> +					opp-supported-hw = <0x04>;
> +				};
> +
>   				opp-800000000 {
>   					opp-hz = /bits/ 64 <800000000>;
>   					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
>   					opp-peak-kBps = <8532000>;
> +					opp-supported-hw = <0x07>;
>   				};
>   
>   				opp-650000000 {
>   					opp-hz = /bits/ 64 <650000000>;
>   					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
>   					opp-peak-kBps = <7216000>;
> +					opp-supported-hw = <0x07>;
>   				};
>   
>   				opp-565000000 {
>   					opp-hz = /bits/ 64 <565000000>;
>   					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
>   					opp-peak-kBps = <5412000>;
> +					opp-supported-hw = <0x07>;
>   				};
>   
>   				opp-430000000 {
>   					opp-hz = /bits/ 64 <430000000>;
>   					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
>   					opp-peak-kBps = <5412000>;
> +					opp-supported-hw = <0x07>;
>   				};
>   
>   				opp-355000000 {
>   					opp-hz = /bits/ 64 <355000000>;
>   					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
>   					opp-peak-kBps = <3072000>;
> +					opp-supported-hw = <0x07>;
>   				};
>   
>   				opp-267000000 {
>   					opp-hz = /bits/ 64 <267000000>;
>   					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
>   					opp-peak-kBps = <3072000>;
> +					opp-supported-hw = <0x07>;
>   				};
>   
>   				opp-180000000 {
>   					opp-hz = /bits/ 64 <180000000>;
>   					opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
>   					opp-peak-kBps = <1804000>;
> +					opp-supported-hw = <0x07>;
>   				};
>   			};
>   		};
> 

A gentle ping.

-Akhil.
diff mbox series

Patch

diff --git a/arch/arm64/boot/dts/qcom/sc7180.dtsi b/arch/arm64/boot/dts/qcom/sc7180.dtsi
index 6678f1e..8cae3eb 100644
--- a/arch/arm64/boot/dts/qcom/sc7180.dtsi
+++ b/arch/arm64/boot/dts/qcom/sc7180.dtsi
@@ -675,6 +675,11 @@ 
 				reg = <0x25b 0x1>;
 				bits = <1 3>;
 			};
+
+			gpu_speed_bin: gpu_speed_bin@1d2 {
+				reg = <0x1d2 0x2>;
+				bits = <5 8>;
+			};
 		};
 
 		sdhc_1: sdhci@7c4000 {
@@ -1907,52 +1912,69 @@ 
 			operating-points-v2 = <&gpu_opp_table>;
 			qcom,gmu = <&gmu>;
 
+			nvmem-cells = <&gpu_speed_bin>;
+			nvmem-cell-names = "speed_bin";
+
 			interconnects = <&gem_noc MASTER_GFX3D 0 &mc_virt SLAVE_EBI1 0>;
 			interconnect-names = "gfx-mem";
 
 			gpu_opp_table: opp-table {
 				compatible = "operating-points-v2";
 
+				opp-825000000 {
+					opp-hz = /bits/ 64 <825000000>;
+					opp-level = <RPMH_REGULATOR_LEVEL_TURBO_L1>;
+					opp-peak-kBps = <8532000>;
+					opp-supported-hw = <0x04>;
+				};
+
 				opp-800000000 {
 					opp-hz = /bits/ 64 <800000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_TURBO>;
 					opp-peak-kBps = <8532000>;
+					opp-supported-hw = <0x07>;
 				};
 
 				opp-650000000 {
 					opp-hz = /bits/ 64 <650000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_NOM_L1>;
 					opp-peak-kBps = <7216000>;
+					opp-supported-hw = <0x07>;
 				};
 
 				opp-565000000 {
 					opp-hz = /bits/ 64 <565000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_NOM>;
 					opp-peak-kBps = <5412000>;
+					opp-supported-hw = <0x07>;
 				};
 
 				opp-430000000 {
 					opp-hz = /bits/ 64 <430000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS_L1>;
 					opp-peak-kBps = <5412000>;
+					opp-supported-hw = <0x07>;
 				};
 
 				opp-355000000 {
 					opp-hz = /bits/ 64 <355000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_SVS>;
 					opp-peak-kBps = <3072000>;
+					opp-supported-hw = <0x07>;
 				};
 
 				opp-267000000 {
 					opp-hz = /bits/ 64 <267000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_LOW_SVS>;
 					opp-peak-kBps = <3072000>;
+					opp-supported-hw = <0x07>;
 				};
 
 				opp-180000000 {
 					opp-hz = /bits/ 64 <180000000>;
 					opp-level = <RPMH_REGULATOR_LEVEL_MIN_SVS>;
 					opp-peak-kBps = <1804000>;
+					opp-supported-hw = <0x07>;
 				};
 			};
 		};