Message ID | 1619838819-11309-2-git-send-email-yongqiang.niu@mediatek.com (mailing list archive) |
---|---|
State | New, archived |
Headers | show |
Series | move page flip handle into cmdq cb | expand |
Hi, Yongqiang: Yongqiang Niu <yongqiang.niu@mediatek.com> 於 2021年5月1日 週六 上午11:13寫道: > > move page flip handle into cmdq cb > irq callback will before cmdq flush ddp register > into hardware, that will cause the display frame page > flip event before it realy display out time After apply patch [1], we don't need to care about which one (irq or cmdq_cb) come first. Even though cmdq_cb come later, GCE would have already write register in vblank. [1] https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/commit/?h=next-20210430&id=368166ec7600ba83587cfcb31d817cf6479cf006 Regards, Chun-Kuang. > > Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> > --- > drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 46 ++++++++++++++++++++++++++++++--- > 1 file changed, 43 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > index 8b0de90..c37881b 100644 > --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c > @@ -72,6 +72,13 @@ struct mtk_crtc_state { > unsigned int pending_vrefresh; > }; > > +#if IS_REACHABLE(CONFIG_MTK_CMDQ) > +struct mtk_cmdq_cb_data { > + struct cmdq_pkt *cmdq_handle; > + struct mtk_drm_crtc *mtk_crtc; > +}; > +#endif > + > static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c) > { > return container_of(c, struct mtk_drm_crtc, base); > @@ -96,7 +103,6 @@ static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) > > static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) > { > - drm_crtc_handle_vblank(&mtk_crtc->base); > if (mtk_crtc->pending_needs_vblank) { > mtk_drm_crtc_finish_page_flip(mtk_crtc); > mtk_crtc->pending_needs_vblank = false; > @@ -223,7 +229,27 @@ struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc, > #if IS_REACHABLE(CONFIG_MTK_CMDQ) > static void ddp_cmdq_cb(struct cmdq_cb_data data) > { > - cmdq_pkt_destroy(data.data); > + struct mtk_cmdq_cb_data *cb_data = data.data; > + struct mtk_drm_crtc *mtk_crtc; > + > + if (!cb_data) { > + DRM_ERROR("cmdq callback data is null pointer!\n"); > + return; > + } > + > + mtk_crtc = cb_data->mtk_crtc; > + if (!mtk_crtc) { > + DRM_ERROR("cmdq callback mtk_crtc is null pointer!\n"); > + goto destroy_pkt; > + } > + > + mtk_drm_finish_page_flip(mtk_crtc); > + > +destroy_pkt: > + if (cb_data->cmdq_handle) > + cmdq_pkt_destroy(cb_data->cmdq_handle); > + > + kfree(cb_data); > } > #endif > > @@ -463,13 +489,20 @@ static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc) > } > #if IS_REACHABLE(CONFIG_MTK_CMDQ) > if (mtk_crtc->cmdq_client) { > + struct mtk_cmdq_cb_data *cb_data; > + > mbox_flush(mtk_crtc->cmdq_client->chan, 2000); > cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE); > cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event); > cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false); > mtk_crtc_ddp_config(crtc, cmdq_handle); > cmdq_pkt_finalize(cmdq_handle); > - cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cmdq_handle); > + > + cb_data = kmalloc(sizeof(*cb_data), GFP_KERNEL); > + cb_data->cmdq_handle = cmdq_handle; > + cb_data->mtk_crtc = mtk_crtc; > + > + cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cb_data); > } > #endif > mutex_unlock(&mtk_crtc->hw_lock); > @@ -488,7 +521,14 @@ static void mtk_crtc_ddp_irq(void *data) > #endif > mtk_crtc_ddp_config(crtc, NULL); > > + drm_crtc_handle_vblank(&mtk_crtc->base); > + > +#if IS_REACHABLE(CONFIG_MTK_CMDQ) > + if (!priv->data->shadow_register && !mtk_crtc->cmdq_client) > + mtk_drm_finish_page_flip(mtk_crtc); > +#else > mtk_drm_finish_page_flip(mtk_crtc); > +#endif > } > > static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc) > -- > 1.8.1.1.dirty >
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c index 8b0de90..c37881b 100644 --- a/drivers/gpu/drm/mediatek/mtk_drm_crtc.c +++ b/drivers/gpu/drm/mediatek/mtk_drm_crtc.c @@ -72,6 +72,13 @@ struct mtk_crtc_state { unsigned int pending_vrefresh; }; +#if IS_REACHABLE(CONFIG_MTK_CMDQ) +struct mtk_cmdq_cb_data { + struct cmdq_pkt *cmdq_handle; + struct mtk_drm_crtc *mtk_crtc; +}; +#endif + static inline struct mtk_drm_crtc *to_mtk_crtc(struct drm_crtc *c) { return container_of(c, struct mtk_drm_crtc, base); @@ -96,7 +103,6 @@ static void mtk_drm_crtc_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) static void mtk_drm_finish_page_flip(struct mtk_drm_crtc *mtk_crtc) { - drm_crtc_handle_vblank(&mtk_crtc->base); if (mtk_crtc->pending_needs_vblank) { mtk_drm_crtc_finish_page_flip(mtk_crtc); mtk_crtc->pending_needs_vblank = false; @@ -223,7 +229,27 @@ struct mtk_ddp_comp *mtk_drm_ddp_comp_for_plane(struct drm_crtc *crtc, #if IS_REACHABLE(CONFIG_MTK_CMDQ) static void ddp_cmdq_cb(struct cmdq_cb_data data) { - cmdq_pkt_destroy(data.data); + struct mtk_cmdq_cb_data *cb_data = data.data; + struct mtk_drm_crtc *mtk_crtc; + + if (!cb_data) { + DRM_ERROR("cmdq callback data is null pointer!\n"); + return; + } + + mtk_crtc = cb_data->mtk_crtc; + if (!mtk_crtc) { + DRM_ERROR("cmdq callback mtk_crtc is null pointer!\n"); + goto destroy_pkt; + } + + mtk_drm_finish_page_flip(mtk_crtc); + +destroy_pkt: + if (cb_data->cmdq_handle) + cmdq_pkt_destroy(cb_data->cmdq_handle); + + kfree(cb_data); } #endif @@ -463,13 +489,20 @@ static void mtk_drm_crtc_hw_config(struct mtk_drm_crtc *mtk_crtc) } #if IS_REACHABLE(CONFIG_MTK_CMDQ) if (mtk_crtc->cmdq_client) { + struct mtk_cmdq_cb_data *cb_data; + mbox_flush(mtk_crtc->cmdq_client->chan, 2000); cmdq_handle = cmdq_pkt_create(mtk_crtc->cmdq_client, PAGE_SIZE); cmdq_pkt_clear_event(cmdq_handle, mtk_crtc->cmdq_event); cmdq_pkt_wfe(cmdq_handle, mtk_crtc->cmdq_event, false); mtk_crtc_ddp_config(crtc, cmdq_handle); cmdq_pkt_finalize(cmdq_handle); - cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cmdq_handle); + + cb_data = kmalloc(sizeof(*cb_data), GFP_KERNEL); + cb_data->cmdq_handle = cmdq_handle; + cb_data->mtk_crtc = mtk_crtc; + + cmdq_pkt_flush_async(cmdq_handle, ddp_cmdq_cb, cb_data); } #endif mutex_unlock(&mtk_crtc->hw_lock); @@ -488,7 +521,14 @@ static void mtk_crtc_ddp_irq(void *data) #endif mtk_crtc_ddp_config(crtc, NULL); + drm_crtc_handle_vblank(&mtk_crtc->base); + +#if IS_REACHABLE(CONFIG_MTK_CMDQ) + if (!priv->data->shadow_register && !mtk_crtc->cmdq_client) + mtk_drm_finish_page_flip(mtk_crtc); +#else mtk_drm_finish_page_flip(mtk_crtc); +#endif } static int mtk_drm_crtc_enable_vblank(struct drm_crtc *crtc)
move page flip handle into cmdq cb irq callback will before cmdq flush ddp register into hardware, that will cause the display frame page flip event before it realy display out time Signed-off-by: Yongqiang Niu <yongqiang.niu@mediatek.com> --- drivers/gpu/drm/mediatek/mtk_drm_crtc.c | 46 ++++++++++++++++++++++++++++++--- 1 file changed, 43 insertions(+), 3 deletions(-)