From patchwork Sun Jul 11 06:53:51 2021 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Yongqiang Niu X-Patchwork-Id: 12368997 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-16.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_CR_TRAILER,INCLUDES_PATCH, MAILING_LIST_MULTI,SPF_HELO_NONE,SPF_PASS,UNPARSEABLE_RELAY,USER_AGENT_GIT autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26568C07E96 for ; Sun, 11 Jul 2021 06:54:04 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id B98D86128B for ; Sun, 11 Jul 2021 06:54:02 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org B98D86128B Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=mediatek.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=dri-devel-bounces@lists.freedesktop.org Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 37138897E3; Sun, 11 Jul 2021 06:54:02 +0000 (UTC) Received: from mailgw01.mediatek.com (unknown [60.244.123.138]) by gabe.freedesktop.org (Postfix) with ESMTPS id 5968189991 for ; Sun, 11 Jul 2021 06:54:01 +0000 (UTC) X-UUID: e14a25b030b544668773146215d51956-20210711 X-UUID: e14a25b030b544668773146215d51956-20210711 Received: from mtkcas10.mediatek.inc [(172.21.101.39)] by mailgw01.mediatek.com (envelope-from ) (Generic MTA with TLSv1.2 ECDHE-RSA-AES256-SHA384 256/256) with ESMTP id 1654619029; Sun, 11 Jul 2021 14:53:57 +0800 Received: from mtkcas11.mediatek.inc (172.21.101.40) by mtkmbs02n1.mediatek.inc (172.21.101.77) with Microsoft SMTP Server (TLS) id 15.0.1497.2; Sun, 11 Jul 2021 14:53:55 +0800 Received: from localhost.localdomain (10.17.3.153) by mtkcas11.mediatek.inc (172.21.101.73) with Microsoft SMTP Server id 15.0.1497.2 via Frontend Transport; Sun, 11 Jul 2021 14:53:54 +0800 From: Yongqiang Niu To: Chun-Kuang Hu Subject: [PATCH v3] drm/mediatek: adjust rdma fifo threshold calculate formula Date: Sun, 11 Jul 2021 14:53:51 +0800 Message-ID: <1625986431-27399-2-git-send-email-yongqiang.niu@mediatek.com> X-Mailer: git-send-email 1.8.1.1.dirty In-Reply-To: <1625986431-27399-1-git-send-email-yongqiang.niu@mediatek.com> References: <1625986431-27399-1-git-send-email-yongqiang.niu@mediatek.com> MIME-Version: 1.0 X-MTK: N X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: devicetree@vger.kernel.org, Project_Global_Chrome_Upstream_Group@mediatek.com, David Airlie , Jassi Brar , linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, Yongqiang Niu , Dennis YC Hsieh , Fabien Parent , Rob Herring , linux-mediatek@lists.infradead.org, Hsin-Yi Wang , Matthias Brugger , linux-arm-kernel@lists.infradead.org Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" the orginal formula will caused rdma fifo threshold config overflow and no one could come out a solution for all SoC, set threshold to 70% of max fifo size to make sure it will not overflow, and 70% is a empirical vlaue Signed-off-by: Yongqiang Niu --- drivers/gpu/drm/mediatek/mtk_disp_rdma.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c index f123fc0..f1f6a2e 100644 --- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c +++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c @@ -164,10 +164,10 @@ void mtk_rdma_config(struct device *dev, unsigned int width, /* * Enable FIFO underflow since DSI and DPI can't be blocked. * Keep the FIFO pseudo size reset default of 8 KiB. Set the - * output threshold to 6 microseconds with 7/6 overhead to - * account for blanking, and with a pixel depth of 4 bytes: + * output threshold to 70% of max fifo size to make sure the + * threhold will not overflow */ - threshold = width * height * vrefresh * 4 * 7 / 1000000; + threshold = rdma_fifo_size * 7 / 10; reg = RDMA_FIFO_UNDERFLOW_EN | RDMA_FIFO_PSEUDO_SIZE(rdma_fifo_size) | RDMA_OUTPUT_VALID_FIFO_THRESHOLD(threshold);