diff mbox series

[v10,01/15] drm/msm/disp/dpu: cache crtc obj in the dpu_encoder during initialization

Message ID 1671721502-16587-2-git-send-email-quic_vpolimer@quicinc.com (mailing list archive)
State New, archived
Headers show
Series Add PSR support for eDP | expand

Commit Message

Vinod Polimera Dec. 22, 2022, 3:04 p.m. UTC 
Cache crtc obj in the dpu encoder during initialization.
This will avoid extracting crtc from connector state there by
simplifying the obj access whenever it is required.

This patch is dependent on the series:
https://patchwork.freedesktop.org/series/110969/

Signed-off-by: Vinod Polimera <quic_vpolimer@quicinc.com>
---
 drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c    |  4 ----
 drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 16 +++++-----------
 drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c     |  1 +
 3 files changed, 6 insertions(+), 15 deletions(-)
diff mbox series

Patch

diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
index 3f72d38..289d51e 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c
@@ -1029,7 +1029,6 @@  static void dpu_crtc_disable(struct drm_crtc *crtc,
 		 */
 		if (dpu_encoder_get_intf_mode(encoder) == INTF_MODE_VIDEO)
 			release_bandwidth = true;
-		dpu_encoder_assign_crtc(encoder, NULL);
 	}
 
 	/* wait for frame_event_done completion */
@@ -1099,9 +1098,6 @@  static void dpu_crtc_enable(struct drm_crtc *crtc,
 	trace_dpu_crtc_enable(DRMID(crtc), true, dpu_crtc);
 	dpu_crtc->enabled = true;
 
-	drm_for_each_encoder_mask(encoder, crtc->dev, crtc->state->encoder_mask)
-		dpu_encoder_assign_crtc(encoder, crtc);
-
 	/* Enable/restore vblank irq handling */
 	drm_crtc_vblank_on(crtc);
 }
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
index a585036..5055d56 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c
@@ -1317,7 +1317,6 @@  static void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc,
 		struct dpu_encoder_phys *phy_enc)
 {
 	struct dpu_encoder_virt *dpu_enc = NULL;
-	unsigned long lock_flags;
 
 	if (!drm_enc || !phy_enc)
 		return;
@@ -1325,12 +1324,11 @@  static void dpu_encoder_vblank_callback(struct drm_encoder *drm_enc,
 	DPU_ATRACE_BEGIN("encoder_vblank_callback");
 	dpu_enc = to_dpu_encoder_virt(drm_enc);
 
-	atomic_inc(&phy_enc->vsync_cnt);
+	if (!dpu_enc->crtc)
+		return;
 
-	spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
-	if (dpu_enc->crtc)
-		dpu_crtc_vblank_callback(dpu_enc->crtc);
-	spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
+	atomic_inc(&phy_enc->vsync_cnt);
+	dpu_crtc_vblank_callback(dpu_enc->crtc);
 
 	DPU_ATRACE_END("encoder_vblank_callback");
 }
@@ -1369,17 +1367,13 @@  void dpu_encoder_toggle_vblank_for_crtc(struct drm_encoder *drm_enc,
 					struct drm_crtc *crtc, bool enable)
 {
 	struct dpu_encoder_virt *dpu_enc = to_dpu_encoder_virt(drm_enc);
-	unsigned long lock_flags;
 	int i;
 
 	trace_dpu_enc_vblank_cb(DRMID(drm_enc), enable);
 
-	spin_lock_irqsave(&dpu_enc->enc_spinlock, lock_flags);
-	if (dpu_enc->crtc != crtc) {
-		spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
+	if (!dpu_enc->crtc || dpu_enc->crtc != crtc) {
 		return;
 	}
-	spin_unlock_irqrestore(&dpu_enc->enc_spinlock, lock_flags);
 
 	for (i = 0; i < dpu_enc->num_phys_encs; i++) {
 		struct dpu_encoder_phys *phys = dpu_enc->phys_encs[i];
diff --git a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
index 93221a2..264d571 100644
--- a/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
+++ b/drivers/gpu/drm/msm/disp/dpu1/dpu_kms.c
@@ -801,6 +801,7 @@  static int _dpu_kms_drm_obj_init(struct dpu_kms *dpu_kms)
 		}
 		priv->crtcs[priv->num_crtcs++] = crtc;
 		encoder->possible_crtcs = 1 << drm_crtc_index(crtc);
+		dpu_encoder_assign_crtc(encoder, crtc);
 		i++;
 	}