| Message ID | 1711656246-3483-1-git-send-email-quic_khsieh@quicinc.com (mailing list archive) |
|---|---|
| State | New, archived |
| Headers | show |
| Series | [v1] drm/msm/dp: assign correct DP controller ID to interface table | expand |
On 3/28/2024 1:04 PM, Kuogee Hsieh wrote: > At current x1e80100 interface table, interface #3 is wrongly > connected to DP controller #0 and interface #4 wrongly connected > to DP controller #2. Fix this problem by connect Interface #3 to > DP controller #0 and interface #4 connect to DP controller #1. > Also add interface #6, #7 and #8 connections to DP controller to > complete x1e80100 interface table. > > Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> > --- > .../drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 34 ++++++++++++++++++++-- > 1 file changed, 31 insertions(+), 3 deletions(-) > Fixes: e3b1f369db5a ("drm/msm/dpu: Add X1E80100 support") I cross-checked all the entries and this looks right. Thanks for fixing this. Reviewed-by: Abhinav Kumar <quic_abhinavk@quicinc.com>
On 24-03-28 13:04:05, Kuogee Hsieh wrote: > At current x1e80100 interface table, interface #3 is wrongly > connected to DP controller #0 and interface #4 wrongly connected > to DP controller #2. Fix this problem by connect Interface #3 to > DP controller #0 and interface #4 connect to DP controller #1. > Also add interface #6, #7 and #8 connections to DP controller to > complete x1e80100 interface table. > > Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> > --- Nitpick: Probably mention the x1e80100 in the subject line somehow. Reviewed-by: Abel Vesa <abel.vesa@linaro.org> > .../drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 34 ++++++++++++++++++++-- > 1 file changed, 31 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h > index 9a9f709..a3e60ac 100644 > --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h > +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h > @@ -324,6 +324,7 @@ static const struct dpu_wb_cfg x1e80100_wb[] = { > }, > }; > > +/* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */ > static const struct dpu_intf_cfg x1e80100_intf[] = { > { > .name = "intf_0", .id = INTF_0, > @@ -358,8 +359,8 @@ static const struct dpu_intf_cfg x1e80100_intf[] = { > .name = "intf_3", .id = INTF_3, > .base = 0x37000, .len = 0x280, > .features = INTF_SC7280_MASK, > - .type = INTF_DP, > - .controller_id = MSM_DP_CONTROLLER_1, > + .type = INTF_NONE, > + .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ > .prog_fetch_lines_worst_case = 24, > .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), > .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), > @@ -368,7 +369,7 @@ static const struct dpu_intf_cfg x1e80100_intf[] = { > .base = 0x38000, .len = 0x280, > .features = INTF_SC7280_MASK, > .type = INTF_DP, > - .controller_id = MSM_DP_CONTROLLER_2, > + .controller_id = MSM_DP_CONTROLLER_1, > .prog_fetch_lines_worst_case = 24, > .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20), > .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21), > @@ -381,6 +382,33 @@ static const struct dpu_intf_cfg x1e80100_intf[] = { > .prog_fetch_lines_worst_case = 24, > .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22), > .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23), > + }, { > + .name = "intf_6", .id = INTF_6, > + .base = 0x3A000, .len = 0x280, > + .features = INTF_SC7280_MASK, > + .type = INTF_DP, > + .controller_id = MSM_DP_CONTROLLER_2, > + .prog_fetch_lines_worst_case = 24, > + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17), > + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16), > + }, { > + .name = "intf_7", .id = INTF_7, > + .base = 0x3b000, .len = 0x280, > + .features = INTF_SC7280_MASK, > + .type = INTF_NONE, > + .controller_id = MSM_DP_CONTROLLER_2, /* pair with intf_6 for DP MST */ > + .prog_fetch_lines_worst_case = 24, > + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18), > + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19), > + }, { > + .name = "intf_8", .id = INTF_8, > + .base = 0x3c000, .len = 0x280, > + .features = INTF_SC7280_MASK, > + .type = INTF_NONE, > + .controller_id = MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */ > + .prog_fetch_lines_worst_case = 24, > + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), > + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), > }, > }; > > -- > 2.7.4 >
diff --git a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h index 9a9f709..a3e60ac 100644 --- a/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h +++ b/drivers/gpu/drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h @@ -324,6 +324,7 @@ static const struct dpu_wb_cfg x1e80100_wb[] = { }, }; +/* TODO: INTF 3, 8 and 7 are used for MST, marked as INTF_NONE for now */ static const struct dpu_intf_cfg x1e80100_intf[] = { { .name = "intf_0", .id = INTF_0, @@ -358,8 +359,8 @@ static const struct dpu_intf_cfg x1e80100_intf[] = { .name = "intf_3", .id = INTF_3, .base = 0x37000, .len = 0x280, .features = INTF_SC7280_MASK, - .type = INTF_DP, - .controller_id = MSM_DP_CONTROLLER_1, + .type = INTF_NONE, + .controller_id = MSM_DP_CONTROLLER_0, /* pair with intf_0 for DP MST */ .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 30), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 31), @@ -368,7 +369,7 @@ static const struct dpu_intf_cfg x1e80100_intf[] = { .base = 0x38000, .len = 0x280, .features = INTF_SC7280_MASK, .type = INTF_DP, - .controller_id = MSM_DP_CONTROLLER_2, + .controller_id = MSM_DP_CONTROLLER_1, .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 20), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 21), @@ -381,6 +382,33 @@ static const struct dpu_intf_cfg x1e80100_intf[] = { .prog_fetch_lines_worst_case = 24, .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 22), .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 23), + }, { + .name = "intf_6", .id = INTF_6, + .base = 0x3A000, .len = 0x280, + .features = INTF_SC7280_MASK, + .type = INTF_DP, + .controller_id = MSM_DP_CONTROLLER_2, + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 17), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 16), + }, { + .name = "intf_7", .id = INTF_7, + .base = 0x3b000, .len = 0x280, + .features = INTF_SC7280_MASK, + .type = INTF_NONE, + .controller_id = MSM_DP_CONTROLLER_2, /* pair with intf_6 for DP MST */ + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 18), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 19), + }, { + .name = "intf_8", .id = INTF_8, + .base = 0x3c000, .len = 0x280, + .features = INTF_SC7280_MASK, + .type = INTF_NONE, + .controller_id = MSM_DP_CONTROLLER_1, /* pair with intf_4 for DP MST */ + .prog_fetch_lines_worst_case = 24, + .intr_underrun = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 12), + .intr_vsync = DPU_IRQ_IDX(MDP_SSPP_TOP0_INTR, 13), }, };
At current x1e80100 interface table, interface #3 is wrongly connected to DP controller #0 and interface #4 wrongly connected to DP controller #2. Fix this problem by connect Interface #3 to DP controller #0 and interface #4 connect to DP controller #1. Also add interface #6, #7 and #8 connections to DP controller to complete x1e80100 interface table. Signed-off-by: Kuogee Hsieh <quic_khsieh@quicinc.com> --- .../drm/msm/disp/dpu1/catalog/dpu_9_2_x1e80100.h | 34 ++++++++++++++++++++-- 1 file changed, 31 insertions(+), 3 deletions(-)