From patchwork Tue Feb 17 10:32:24 2015 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Sascha Hauer X-Patchwork-Id: 5838211 Return-Path: X-Original-To: patchwork-dri-devel@patchwork.kernel.org Delivered-To: patchwork-parsemail@patchwork1.web.kernel.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.136]) by patchwork1.web.kernel.org (Postfix) with ESMTP id 74A5E9F380 for ; Tue, 17 Feb 2015 10:32:50 +0000 (UTC) Received: from mail.kernel.org (localhost [127.0.0.1]) by mail.kernel.org (Postfix) with ESMTP id 8879020154 for ; Tue, 17 Feb 2015 10:32:49 +0000 (UTC) Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) by mail.kernel.org (Postfix) with ESMTP id 8616B20148 for ; Tue, 17 Feb 2015 10:32:48 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id D048C6E21C; Tue, 17 Feb 2015 02:32:47 -0800 (PST) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from metis.ext.pengutronix.de (metis.ext.pengutronix.de [92.198.50.35]) by gabe.freedesktop.org (Postfix) with ESMTP id ECBA86E18E for ; Tue, 17 Feb 2015 02:32:45 -0800 (PST) Received: from ptx.hi.pengutronix.de ([2001:67c:670:100:1d::c0] ident=Debian-exim) by metis.ext.pengutronix.de with esmtp (Exim 4.72) (envelope-from ) id 1YNfSB-0001jk-IC; Tue, 17 Feb 2015 11:32:31 +0100 Received: from sha by ptx.hi.pengutronix.de with local (Exim 4.80) (envelope-from ) id 1YNfS4-0001Yr-Jz; Tue, 17 Feb 2015 11:32:24 +0100 Date: Tue, 17 Feb 2015 11:32:24 +0100 From: Sascha Hauer To: Tomi Valkeinen Subject: Re: [PATCH RFC v9 01/20] clk: divider: Correct parent clk round rate if no bestdiv is normally found Message-ID: <20150217103224.GS12209@pengutronix.de> References: <1423720903-24806-1-git-send-email-Ying.Liu@freescale.com> <1423720903-24806-2-git-send-email-Ying.Liu@freescale.com> <20150212093356.GR12209@pengutronix.de> <20150212103944.GA1290@victor> <20150212122405.GW12209@pengutronix.de> <20150212125646.GT8656@n2100.arm.linux.org.uk> <20150212134131.GX12209@pengutronix.de> <54DE0BB8.7070004@ti.com> <20150213185713.GA12209@pengutronix.de> <54E1D1F5.2050603@ti.com> MIME-Version: 1.0 Content-Disposition: inline In-Reply-To: <54E1D1F5.2050603@ti.com> X-Sent-From: Pengutronix Hildesheim X-URL: http://www.pengutronix.de/ X-IRC: #ptxdist @freenode X-Accept-Language: de,en X-Accept-Content-Type: text/plain X-Uptime: 11:24:30 up 124 days, 21:38, 69 users, load average: 0.00, 0.03, 0.05 User-Agent: Mutt/1.5.21 (2010-09-15) X-SA-Exim-Connect-IP: 2001:67c:670:100:1d::c0 X-SA-Exim-Mail-From: sha@pengutronix.de X-SA-Exim-Scanned: No (on metis.ext.pengutronix.de); SAEximRunCond expanded to false X-PTX-Original-Recipient: dri-devel@lists.freedesktop.org Cc: stefan.wahren@i2se.com, devicetree@vger.kernel.org, Russell King - ARM Linux , mturquette@linaro.org, sboyd@codeaurora.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, a.hajda@samsung.com, kernel@pengutronix.de, andy.yan@rock-chips.com, linux-arm-kernel@lists.infradead.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Spam-Status: No, score=-4.2 required=5.0 tests=BAYES_00, RCVD_IN_DNSWL_MED, T_RP_MATCHES_RCVD, UNPARSEABLE_RELAY autolearn=unavailable version=3.3.1 X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on mail.kernel.org X-Virus-Scanned: ClamAV using ClamSMTP On Mon, Feb 16, 2015 at 01:18:13PM +0200, Tomi Valkeinen wrote: > On 13/02/15 20:57, Sascha Hauer wrote: > > On Fri, Feb 13, 2015 at 04:35:36PM +0200, Tomi Valkeinen wrote: > >> On 12/02/15 15:41, Sascha Hauer wrote: > >> > >>> Tomis patch is based on the assumption that clk_set_rate(clk_round_rate(rate)) > >>> is equal to clk_round_rate(rate). So when this assumption is wrong then > >>> it should simply be reverted. > >> > >> When is it not equal? > >> > >> I agree that doing clk_set_rate(clk, clk_round_rate(clk, rate)) is > >> pointless, but shouldn't it still work? > >> > >> And we can forget about clk_round_rate. Without my patch, this would > >> behave oddly also: > >> > >> rate = clk_get_rate(clk); > >> clk_set_rate(clk, rate); > >> > >> The end result could be something else than 'rate'. > > > > I agree that it's a bit odd, but I think it has to be like this. > > Consider that you request a rate of 100Hz, but the clock can only > > produce 99.5Hz, so due to rounding clk_round_rate() returns 99Hz. > > Now when you request 99Hz from clk_set_rate() the 99.5Hz value > > can't be used because it's too high. > > Would that problem better be fixed by changing the clock driver so that > when asked for 99Hz, it would look for rates less than 100Hz? > > I think the old behavior was so odd that I would call it broken, so I > hope the current problems can be fixed via some other ways than breaking > it again. I gave it a try, but so far I have no idea how to implement the divider correctly and bullet proof. What I have so far is a test which creates some cascaded dividers and sets rates on them. The test iterates over the frequency range and a) calls clk_round_rate with the iterator, b) sets the clk to the iterator, c) sets the clk to the rounded rate. Be prepared for surprises and try to fix the results... I failed for now and wonder if the approach to the divider is wrong. Sascha From 58a46b16d4b67d5cd7df4af6deb5b96e19afe230 Mon Sep 17 00:00:00 2001 From: Sascha Hauer Date: Tue, 17 Feb 2015 11:24:10 +0100 Subject: [PATCH] clk: clk-divider: Add a simple test for dividers Signed-off-by: Sascha Hauer --- drivers/clk/clk-divider.c | 86 +++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 86 insertions(+) diff --git a/drivers/clk/clk-divider.c b/drivers/clk/clk-divider.c index c0a842b..cd66625 100644 --- a/drivers/clk/clk-divider.c +++ b/drivers/clk/clk-divider.c @@ -463,3 +463,89 @@ struct clk *clk_register_divider_table(struct device *dev, const char *name, width, clk_divider_flags, table, lock); } EXPORT_SYMBOL_GPL(clk_register_divider_table); + +/* + * Simple test of dividers. Try to set rates between 1 and 10000Hz and + * - get output of clk_round_rate() + * - set the current target rate, get the rate + * - set the rate to the rounded rate, get the rate + * + * Whenever a value changed print the results + */ +static void clktest_one(struct clk *clk) +{ + int i, ret; + unsigned long roundsetrate, last_roundsetrate = 0; + unsigned long roundrate, last_roundrate = 0; + unsigned long setrate, last_setrate = 0; + + for (i = 1; i < 10000; i++) { + roundrate = clk_round_rate(clk, i); + + clk_set_rate(clk, i); + setrate = clk_get_rate(clk); + + ret = clk_set_rate(clk, roundrate); + if (ret) { + printk("clkdivtest: Failed to set rate: %d\n", ret); + return; + } + + roundsetrate = clk_get_rate(clk); + + if (last_roundsetrate != roundsetrate || + last_roundrate != roundrate || + last_setrate != setrate) + printk("target rate: %4d rounded: %4ld set: %4ld round/set: %4ld\n", + i, roundrate, setrate, roundsetrate); + + last_roundsetrate = roundsetrate; + last_roundrate = roundrate; + last_setrate = setrate; + } +} + +static int clktest(void) +{ + u32 reg_div1 = 0; + u32 reg_div2 = 0; + u32 reg_div3 = 0; + struct clk *clktest_base = ERR_PTR(-ENODEV); + struct clk *clktest_div1 = ERR_PTR(-ENODEV); + struct clk *clktest_div2 = ERR_PTR(-ENODEV); + struct clk *clktest_div3 = ERR_PTR(-ENODEV); + + clktest_base = clk_register_fixed_rate(NULL, "clktest_base", NULL, 0, 10000); + clktest_div1 = clk_register_divider(NULL, "clktest_div1", "clktest_base", + 0, ®_div1, 0, 4, 0, NULL); + clktest_div2 = clk_register_divider(NULL, "clktest_div2", "clktest_div1", + CLK_SET_RATE_PARENT, ®_div2, 0, 4, 0, NULL); + clktest_div3 = clk_register_divider(NULL, "clktest_div3", "clktest_div2", + CLK_SET_RATE_PARENT, ®_div3, 0, 4, 0, NULL); + + if (IS_ERR(clktest_base) || IS_ERR(clktest_div1) || + IS_ERR(clktest_div2) || IS_ERR(clktest_div3)) { + printk("clkdivtest: Failed to register clocks\n"); + goto err_out; + } + + printk("------------------ Single divider, fin=10000Hz ------------------\n"); + clktest_one(clktest_div1); + printk("--------------- two cascaded dividers, fin=10000Hz --------------\n"); + clktest_one(clktest_div2); + printk("-------------- three cascaded dividers, fin=10000Hz -------------\n"); + clktest_one(clktest_div3); + +err_out: + if (!IS_ERR(clktest_base)) + clk_unregister(clktest_base); + if (!IS_ERR(clktest_div1)) + clk_unregister(clktest_div1); + if (!IS_ERR(clktest_div2)) + clk_unregister(clktest_div2); + if (!IS_ERR(clktest_div3)) + clk_unregister(clktest_div3); + + return 0; +} +late_initcall(clktest);