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[178.190.139.123]) by smtp.gmail.com with ESMTPSA id v2sm41824518wja.41.2016.12.09.03.21.53 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Fri, 09 Dec 2016 03:21:53 -0800 (PST) From: Christian Gmeiner To: dri-devel@lists.freedesktop.org Subject: [PATCH 08/10] drm/etnaviv: make it possible to reconfigure perf counter Date: Fri, 9 Dec 2016 12:21:29 +0100 Message-Id: <20161209112131.3924-9-christian.gmeiner@gmail.com> X-Mailer: git-send-email 2.9.3 In-Reply-To: <20161209112131.3924-1-christian.gmeiner@gmail.com> References: <20161209112131.3924-1-christian.gmeiner@gmail.com> Cc: linux+etnaviv@armlinux.org.uk, cphealy@gmail.com X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP Each perf counter 'unit' consits of a multipler configuration register and a register to read the selected value. Extend the uapi to handle this case gracefully. Before the readback is done the mux (config_reg) get reconfigured (vale). Signed-off-by: Christian Gmeiner --- drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c | 7 +++++-- drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 3 +++ drivers/gpu/drm/etnaviv/etnaviv_gpu.h | 3 +++ include/uapi/drm/etnaviv_drm.h | 6 +++++- 4 files changed, 16 insertions(+), 3 deletions(-) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c b/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c index a69eff7..08f9b3d 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gem_submit.c @@ -298,14 +298,17 @@ static int submit_readback(struct etnaviv_gem_submit *submit, return -EINVAL; } - if (r->flags) { - DRM_ERROR("readback flags not 0"); + if (r->flags > ETNA_READBACK_PERF) { + DRM_ERROR("invalid readback flags"); return -EINVAL; } cmdbuf->readbacks[i].bo_vma = etnaviv_gem_vmap(&bo->obj->base); cmdbuf->readbacks[i].offset = r->readback_offset; cmdbuf->readbacks[i].reg = r->reg; + cmdbuf->readbacks[i].flags = r->flags; + cmdbuf->readbacks[i].perf_reg = r->perf_reg; + cmdbuf->readbacks[i].perf_value = r->perf_value; } return 0; diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c index 2aa1a26..b22212c 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c @@ -1379,6 +1379,9 @@ static void etnaviv_process_readbacks(struct etnaviv_gpu *gpu, const u32 val = gpu_read(gpu, readback->reg); u32 *bo = readback->bo_vma; + if (readback->flags & ETNA_READBACK_PERF) + gpu_write(gpu, readback->perf_reg, readback->perf_value); + *(bo + readback->offset) = val; } } diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.h b/drivers/gpu/drm/etnaviv/etnaviv_gpu.h index 21a4314..02f15c0 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.h +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.h @@ -91,6 +91,9 @@ struct etnaviv_readback { u32 *bo_vma; u32 offset; u32 reg; + u32 flags; + u32 perf_reg; + u32 perf_value; }; struct etnaviv_event { diff --git a/include/uapi/drm/etnaviv_drm.h b/include/uapi/drm/etnaviv_drm.h index 0d30604..f2e24bb 100644 --- a/include/uapi/drm/etnaviv_drm.h +++ b/include/uapi/drm/etnaviv_drm.h @@ -150,11 +150,15 @@ struct drm_etnaviv_gem_submit_bo { __u64 presumed; /* in/out, presumed buffer address */ }; +#define ETNA_READBACK_ONLY 0x0000 +#define ETNA_READBACK_PERF 0x0001 struct drm_etnaviv_gem_submit_readback { __u32 readback_offset;/* in, offset from readback_bo */ __u32 readback_idx; /* in, index of readback_bo buffer */ __u32 reg; /* in, register to read */ - __u32 flags; /* in, needs to be 0 */ + __u32 flags; /* in, ETNA_READBACK_* */ + __u32 perf_reg; /* in, register to write */ + __u32 perf_value; /* in, value to write */ }; /* Each cmdstream submit consists of a table of buffers involved, and