diff mbox

drm: mxsfb: Assure CTRL and CTRL1 values are latched into HW

Message ID 20170226155205.22277-1-marex@denx.de (mailing list archive)
State New, archived
Headers show

Commit Message

Marek Vasut Feb. 26, 2017, 3:52 p.m. UTC
For reasons unknown, the first write into CTRL and CTRL1 registers
is not actually latched into the hardware and the data read back
are the reset values. Second write into the same registers has the
expected effect though and a readback returns the written values.
Add the second write.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Breno Lima <breno.lima@nxp.com>
Cc: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: Dave Airlie <airlied@redhat.com>
Cc: Fabio Estevam <fabio.estevam@nxp.com>
Cc: Stefan Agner <stefan@agner.ch>
---
 drivers/gpu/drm/mxsfb/mxsfb_crtc.c | 2 ++
 1 file changed, 2 insertions(+)
diff mbox

Patch

diff --git a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
index 6d701d2c362d..f02d23d55995 100644
--- a/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
+++ b/drivers/gpu/drm/mxsfb/mxsfb_crtc.c
@@ -84,6 +84,8 @@  static int mxsfb_set_pixel_fmt(struct mxsfb_drm_private *mxsfb)
 
 	writel(ctrl1, mxsfb->base + LCDC_CTRL1);
 	writel(ctrl, mxsfb->base + LCDC_CTRL);
+	writel(ctrl1, mxsfb->base + LCDC_CTRL1);
+	writel(ctrl, mxsfb->base + LCDC_CTRL);
 
 	return 0;
 }