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[91.115.35.97]) by smtp.gmail.com with ESMTPSA id 110sm6593819wra.39.2017.09.12.08.14.02 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Tue, 12 Sep 2017 08:14:06 -0700 (PDT) From: Christian Gmeiner To: dri-devel@lists.freedesktop.org Subject: [PATCH V4 21/23] drm/etnaviv: need to disable clock gating when doing profiling Date: Tue, 12 Sep 2017 17:11:53 +0200 Message-Id: <20170912151155.4603-22-christian.gmeiner@gmail.com> X-Mailer: git-send-email 2.13.5 In-Reply-To: <20170912151155.4603-1-christian.gmeiner@gmail.com> References: <20170912151155.4603-1-christian.gmeiner@gmail.com> Cc: linux+etnaviv@armlinux.org.uk, etnaviv@lists.freedesktop.org, cphealy@gmail.com X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP As done by Vivante kernel driver. Signed-off-by: Christian Gmeiner Reviewed-by: Lucas Stach --- drivers/gpu/drm/etnaviv/etnaviv_gpu.c | 13 +++++++++++++ 1 file changed, 13 insertions(+) diff --git a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c index 842b6642dcd6..04acc3a64c3c 100644 --- a/drivers/gpu/drm/etnaviv/etnaviv_gpu.c +++ b/drivers/gpu/drm/etnaviv/etnaviv_gpu.c @@ -1341,6 +1341,13 @@ static void sync_point_perfmon_sample(struct etnaviv_gpu *gpu, static void sync_point_perfmon_sample_pre(struct etnaviv_gpu *gpu, struct etnaviv_event *event) { + u32 val; + + /* disable clock gating */ + val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); + val &= ~VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; + gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val); + sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_PRE); } @@ -1349,6 +1356,7 @@ static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu, { const struct etnaviv_cmdbuf *cmdbuf = event->cmdbuf; unsigned int i; + u32 val; sync_point_perfmon_sample(gpu, event, ETNA_PM_PROCESS_POST); @@ -1357,6 +1365,11 @@ static void sync_point_perfmon_sample_post(struct etnaviv_gpu *gpu, *pmr->bo_vma = pmr->sequence; } + + /* enable clock gating */ + val = gpu_read(gpu, VIVS_PM_POWER_CONTROLS); + val |= VIVS_PM_POWER_CONTROLS_ENABLE_MODULE_CLOCK_GATING; + gpu_write(gpu, VIVS_PM_POWER_CONTROLS, val); }