From patchwork Thu Sep 28 19:41:42 2017 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Harry Wentland X-Patchwork-Id: 9976795 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 0F1E760375 for ; Thu, 28 Sep 2017 22:13:08 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id E7AC42976C for ; Thu, 28 Sep 2017 22:13:07 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id DADD129771; Thu, 28 Sep 2017 22:13:07 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-3.5 required=2.0 tests=BAD_ENC_HEADER,BAYES_00, DKIM_SIGNED,RCVD_IN_DNSWL_MED,T_DKIM_INVALID,URG_BIZ autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A703E2976C for ; Thu, 28 Sep 2017 22:13:05 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id B88E96E9F0; Thu, 28 Sep 2017 22:13:04 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from NAM02-BL2-obe.outbound.protection.outlook.com (mail-bl2nam02on0071.outbound.protection.outlook.com [104.47.38.71]) by gabe.freedesktop.org (Postfix) with ESMTPS id 65A936E9F0 for ; Thu, 28 Sep 2017 22:13:03 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amdcloud.onmicrosoft.com; s=selector1-amd-com; h=From:Date:Subject:Message-ID:Content-Type:MIME-Version; bh=aWExPIm2x9e3jKsP7GL3WEPLCfbG7HJU5pvf9+aW5N0=; b=2ZE9QPrtnM3MicQwJb5MpnnvCtU7a8PYPUN4C2pWfZN6IuC1TrVezhHFN5JrUEEfbmi01FYodz9gJNLORYgkPcblIzHmgob7Wejt6Z8JkUsr5yi9ME+LeOFlP7dU94HqOeF+DacJpCZjK7E7buPlXq0o3I60Pwq+4N4VYIZ+Yts= Received: from DM5PR12CA0017.namprd12.prod.outlook.com (10.172.32.155) by DM5PR12MB1449.namprd12.prod.outlook.com (10.172.38.138) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.77.7; Thu, 28 Sep 2017 19:41:48 +0000 Received: from BY2NAM03FT052.eop-NAM03.prod.protection.outlook.com (2a01:111:f400:7e4a::203) by DM5PR12CA0017.outlook.office365.com (2603:10b6:4:1::27) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P256) id 15.20.56.11 via Frontend Transport; Thu, 28 Sep 2017 19:41:48 +0000 Authentication-Results: spf=none (sender IP is 165.204.84.17) smtp.mailfrom=amd.com; lists.freedesktop.org; dkim=none (message not signed) header.d=none;lists.freedesktop.org; dmarc=permerror action=none header.from=amd.com; Received-SPF: None (protection.outlook.com: amd.com does not designate permitted sender hosts) Received: from SATLEXCHOV01.amd.com (165.204.84.17) by BY2NAM03FT052.mail.protection.outlook.com (10.152.85.223) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_CBC_SHA384_P384) id 15.20.77.10 via Frontend Transport; Thu, 28 Sep 2017 19:41:48 +0000 Received: from SATLEXDAG01.amd.com (10.181.40.3) by SATLEXCHOV01.amd.com (10.181.40.71) with Microsoft SMTP Server (TLS) id 14.3.361.1; Thu, 28 Sep 2017 14:41:47 -0500 Received: from localhost.localdomain (10.180.168.240) by SATLEXDAG01.amd.com (10.181.40.3) with Microsoft SMTP Server id 14.3.361.1; Thu, 28 Sep 2017 15:41:46 -0400 From: Harry Wentland To: Subject: [PATCH] drm/amd/display: Remove DWB Date: Thu, 28 Sep 2017 15:41:42 -0400 Message-ID: <20170928194142.21061-1-harry.wentland@amd.com> X-Mailer: git-send-email 2.11.0 MIME-Version: 1.0 X-EOPAttributedMessage: 0 X-MS-Office365-Filtering-HT: Tenant X-Forefront-Antispam-Report: CIP:165.204.84.17; IPV:NLI; CTRY:US; EFV:NLI; SFV:NSPM; SFS:(10009020)(6009001)(39860400002)(346002)(376002)(2980300002)(428002)(189002)(199003)(288314003)(33646002)(86362001)(575784001)(39060400002)(48376002)(53946003)(53936002)(49486002)(4326008)(68736007)(16586007)(5660300001)(54906003)(2906002)(50986999)(50226002)(81156014)(47776003)(81166006)(8676002)(6666003)(101416001)(105586002)(6916009)(1076002)(36756003)(305945005)(316002)(50466002)(2351001)(97736004)(356003)(106466001)(77096006)(8936002)(72206003)(5003940100001)(478600001)(189998001)(579004)(19627235001); DIR:OUT; SFP:1101; SCL:1; SRVR:DM5PR12MB1449; H:SATLEXCHOV01.amd.com; FPR:; SPF:None; PTR:InfoDomainNonexistent; MX:1; A:1; LANG:en; X-Microsoft-Exchange-Diagnostics: 1; BY2NAM03FT052; 1:jeW+R/grX3Zwo3VDyFKn2no8WWFfx/VbYMlxVuLAvESgnWjO077rjBGpEUEbB7nVBeB5ANSAjyB9WU8wej3DxE0i6h2XgXfu75GxQX/YY5SZaPj33sQUMr7gYaasxHoL X-MS-PublicTrafficType: Email X-MS-Office365-Filtering-Correlation-Id: e2af8b5d-d141-46c4-4df2-08d506a8f571 X-Microsoft-Antispam: UriScan:; BCL:0; PCL:0; RULEID:(22001)(2017030254152)(2017052603199)(201703131423075)(201703031133081)(201702281549075); SRVR:DM5PR12MB1449; X-Microsoft-Exchange-Diagnostics: 1; DM5PR12MB1449; 3:99voHgAM6hB2mhkKiZLqc5V1vT3smXDib75Is+9MysDMmCyVQNT1ze6fUfyvjbanw8qBEEo2lI9/RAV26X3wq1gHE9rCmpHF1MfH5fIspxfPHJfGCy/a52VkfDPUIl183KXlADMKkXFWs1r7NexXVHMVUUY/hHHTyGv+SGMIhu05HELNbvRYVCAyE7YAndZXf2qGm6wd+A6K+lHinMuSRLdWDyDg97PMjERd6c0+qzzv4fdN6dHSaSIOMxJEGHDE7lW+PJ8IkWnKLcLPMO3SwJZlgbvbokC66DjxwBps0Shmn7Co4Jlz4+cT1HuleQ+Ny9hY8bxz2SX2P588bWxV5g4FPLloEqGut4DE46ZgJDQ=; 25:1plE2w976t527kOHTf6P4QimdFda2Vs6cugVou724OxTjwrnSSmWxqvpqlMa3fbk2CubOHAzmb8HCYWkXNbzE4HqLgrtb6SGIA0nzJ0Gj94XqEbAcKK8HqE/gnjmD9ZdUfXUigIZ74jGo7CiE3gM3H1Y8JyPXCIwBGZY/Av/eYStyaXzYfNvH5a+HREKi1hHeWPNxuSBggvrimWLNYRk9hMs5sAbn76ed8HRBpmHYhnoTPtO1ID2OMovvmgI1yIfh3gxLftGy5BqPrm69zziW4vqmoBBJbfkSUtDbAAShipIm5MFfBMzPUbbF3HxjBsJAupCwdjioVy7AbUVGMQ9qw== X-MS-TrafficTypeDiagnostic: DM5PR12MB1449: X-Microsoft-Exchange-Diagnostics: 1; DM5PR12MB1449; 31:erSqehdfAXzy2c4KEDAopKX+w84eevBdvb4Z5Sq6hz4qTUraaPzP+wZov3At5KIZoQhRN16iFi45kf9xz8alLqujGunG4aR7N0Z5RnaZKbR5gcrXp4p0NBNbrZq46HL1kevHqg53UZ1xMy+h+c+xUMAE8Tdc02eJsQ470dCBv1lMEdksBujmJ52lOKZLTIoVIuMY+981lKNyfwfUrQ0ePOWCxfGg8HxLomiVl3O42UI=; 20:GfsAE8yqMLyEdcF5pWfJst5b0imU5C46RLSnGhT4uhKD5m4loutQpDuRmJeV7HKIjEZN5Rt82DWyDnT8mxHZ63TJ/MF3wDSPO01RPyIaIeNOmYZlBg2eFRw/Ijo2vE3B76+V4p42pEuGBxYVkdDRs3lTZcf3uSgcANZ+KT6tmBtKl0yoEbAcYT0PIpEzj1VpOCncImGQObHRM9bso+gQz/YHHBeUdoq5AnOIlGnw5xTAOljT5cPDStf5vXvOrUFbJQiakbSxY/Q6KHDLiU5+6VKrPCjmcRGLj4xLIyg42+bivb4rYm/imDm1iWvmu4+8Z9M8s6K4IUVm2qfGNi7eNd1WKW1kPw032WBg113PBc/aRP0MXT8f/BNkm/SdrPcHNFGRsgQP2CL7ioxKM5G1HhqPBMXKrGjmdvB9G1SS6qiKgPbxfKK7NmGl36bpF71C7fIyGc9/tJ2g81Tuw3KZqCnNdvDXoBlLWXl01R1P614AtZX2bnqUXS6PrZHoK7ks X-Exchange-Antispam-Report-Test: UriScan:(767451399110); X-Microsoft-Antispam-PRVS: X-Exchange-Antispam-Report-CFA-Test: BCL:0; PCL:0; RULEID:(100000700101)(100105000095)(100000701101)(100105300095)(100000702101)(100105100095)(6040450)(2401047)(8121501046)(5005006)(3002001)(10201501046)(93006095)(93003095)(100000703101)(100105400095)(6055026)(6041248)(20161123562025)(201703131423075)(201702281528075)(201703061421075)(201703061406153)(20161123564025)(20161123558100)(20161123555025)(20161123560025)(6072148)(201708071742011)(100000704101)(100105200095)(100000705101)(100105500095); SRVR:DM5PR12MB1449; BCL:0; PCL:0; RULEID:(100000800101)(100110000095)(100000801101)(100110300095)(100000802101)(100110100095)(100000803101)(100110400095)(100000804101)(100110200095)(100000805101)(100110500095); SRVR:DM5PR12MB1449; X-Microsoft-Exchange-Diagnostics: 1; DM5PR12MB1449; 4:k8Qd6+yWHfd+//p9BqUFBYpnRDyXKp3QKkU3h5/njyyPJXSa720xYNzGRDtOcgFL7bWQLrlW7Jlzq9vqsr04F0kWhZyw2kD3AUIAhMQ3BWx6ikHDYvTzDpY+ASfZ9KnUP7v0ZIWmWInihzwwSPWbvccTdTXQkcvnWeXpZ9Y8fO3sc/g1F3ZxRs2Qg5/4CzktOsNtaa+TZ7ugceCS3McBVV9hhs7aIXkNdtasW1Mium0Cj+y3AD8//2v1742j0fe6uYOSUKiS5xqTHesG0uhPmbsFWpPSSE8P6PfgwHewqxI= X-Forefront-PRVS: 0444EB1997 X-Microsoft-Exchange-Diagnostics: =?us-ascii?Q?1; DM5PR12MB1449; 23:pkG2UYFHWHYqvWRGhqxjOdJ9LjQ5bkU8zarYUt/ID?= =?us-ascii?Q?MufP87oY5MdDYaQymH9HZYAXwU4p/qFa0Y/P8xOtQJzCO+xP6psuMogdtR/H?= =?us-ascii?Q?Wj88f7d9uQdDu69jTrfQmwR3jsP7Mj/yIhUvU/3IVez/1jn07ql3FKl9aBlb?= =?us-ascii?Q?b72YtLlpdcTzw7yYlBTTNPfJt6m4PzL2/9ahq1q1s/f2ISQG5wqO8JJg1ZdR?= =?us-ascii?Q?JKkaBOq6UZwC7CWJcpra97FlQwRV/CWw1QEpSaNNVyYJdNEAv/rHmnmNIppV?= =?us-ascii?Q?3yCGzPCZLv3gzJmzXP7EzvAQbPlEKJGb+FTSprAn5QVrOccLcKEDac4ckDC3?= =?us-ascii?Q?FYX8RzffNCJNcgV7Q2xdHIe04LL25U007qqnfcyBZFtQtPP4ikgG3TZ+BeeD?= =?us-ascii?Q?qdGQ0fNlu7JO/j0EY3v6sfakMq5A42phbeVHM6a0k+VSG25tAatiz0HgJ/8Y?= =?us-ascii?Q?/s+h61XwbYL9Jp4GeTgBcsbHzHIuPN2B9/F1n2W5oz4fNvDzE7zQ2NWsFoAk?= =?us-ascii?Q?Y8NaFCu+4HR3dtkBlwtKo3e8uA+uHcGefOkeIMNGerdkxkzDiJMnskiCgP9M?= =?us-ascii?Q?7HBoFOy04IPmohvxiOWwGN4sjkebWqPXyyDp1+RA1qN0P8bYpC40KXvbAELa?= =?us-ascii?Q?zvRgZOaIFEwn+3fkyB1MJCgHZ8JNeuTjDXO7qbnPO63Hj8RQ+dL1vn5DCbGI?= =?us-ascii?Q?N3IHsjRzj1V7s3cDJDo310vms1uRKCXLeQ3x1R7mTz8nw1u7At0oAGOcKFH9?= =?us-ascii?Q?LCJJBZ2z5F81WDBWXfYGqaVFSWhvUvW//Kbt3+78rdBd11OGQct44butfsx/?= =?us-ascii?Q?vOPDCkUsPY/SmlIAXO9S4sknc/21WgDhQmJrAO1Dd8PeEsDJI6u7sgsU8mEB?= =?us-ascii?Q?MVt8sI+ZjEzhwjKvHYr23mzHCmdoVNkh4qEg+OnPQra8SW0Rhd/tykhtGSjU?= =?us-ascii?Q?dpUL8lDiq2i+Riz+Xpd8Hbnn2X511fXyF9qJUbfW5U/wFMFuSzvH/MJQeuaQ?= =?us-ascii?Q?WvAdYoWGWRvxFlexZ7CRCTuRLNevGipzqhL07h+hwd2K5UT0zOg0fk1yW25k?= =?us-ascii?Q?5vUfCfWwb5G9tyGhXsqpGItf8prk6Y33nFce0uEZCrUAIjFefDkDcqUYspGo?= =?us-ascii?Q?AAIoEbcePSNwVHbPjmq8BJ31GZS3FcCVCOHtCzplXQocNRsc8Q+Y5Z+8W9EA?= =?us-ascii?Q?r15hWXmMbuFFNo=3D?= X-Microsoft-Exchange-Diagnostics: 1; DM5PR12MB1449; 6:hxraI5vszKhhtPHGVkm/SCoQoFsqaDNVmZz5IEP21frG2HzAOKmVgmWHZkWgDm+SKX9KrA6NlTFdxIM/WKRohLprMC6EqxLL1b+Tjzzs/wk2t9QtreACIopcKVXeDoDPaN4rzgT7JOhwYlz2lh0961/MMne00ZwdDcV8gxCedwNPriJaSv60RlKCJlHzsKE02V1lYPkN74Zy15cx9AzxBqY9M0VPtfUjvZcNsLxYcwy8x+E2C5z6W3DAgaIXeNLDC2z97BhuQv1L0onz6+GHFqDqXkfYwbVJQ6y64rF3WF+udjU5Djwpv9dBFTDD5FD550dQ91OxTj11sTrY/u19VQ==; 5:lF1Cz6FbA+q1ajekZNCy56g1hBoehqT9CC3kcRAuLob6MqODk352s+TMWg7XIYogbB4JTQjJH6oAsumq4v5jMaLaLvO9g8xwVEMnm4FuonJr84a9FfoVqAgC3tCgW7fL9V7X1wLiBXn4hXXWwi8PmA==; 24:q9UUp66/7eSzn0zLr66QkXtrz8pzlf7dm0F7fsuzNQv6ecKaYZ8903GLbha45bYa8z7f6+Dd6DB5gjy24eHzuz2J/SQLrDWV0V+vuByqLkQ=; 7:QOROEvHwSOpRyTpceMOYPfbVYSYxwm6oHmg1/XGFOSXkuec5DDciYYAca9vduSJP115PMOcPcIUPW+1+Ezpub2xz4oyzlqtxiBRDwkQw+yi2LWU8zA8oMCVFcim2aEP+Cl+zIA9ww74uA8/25sOPmR+bKJC70oW/Ov4+SSMmpfdw1dAA9/2thJt10uuRZQjIYWyOreiHi81YGc5vafVBOS475Ub7pEUJ3mh3ddYJo0w= SpamDiagnosticOutput: 1:99 SpamDiagnosticMetadata: NSPM X-Microsoft-Exchange-Diagnostics: 1; DM5PR12MB1449; 20:aMYhz3lk0bSAmQZAnv7Jicdc8unhZezG6THB2SsaKmJfAR5sCDtfyiaoiN5hXnr5/QfOHC3SAbkZ89uyI/Zn3JYBNeVNbiJkEZnMsUAiOoe+y9jvH4YLGXIuYdQYPJVXSD1oS8O6ssa7Xsg6CDj8ArK36jZXXE+VAwuhrq6hZwstw+yWwzNwAnzek3qWsoPWBJNuHEsuOA93uvdqYd5pxWyzgRPs8YPTA7pWJYqpZSwzFXhLDsEoOstyLa5JxQA8 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 28 Sep 2017 19:41:48.2408 (UTC) X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d; Ip=[165.204.84.17]; Helo=[SATLEXCHOV01.amd.com] X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM5PR12MB1449 Cc: alexander.deucher@amd.com, tony.cheng@amd.com, dri-devel@lists.freedesktop.org X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP It's not in a good shape and currently completely unused. Signed-off-by: Harry Wentland --- drivers/gpu/drm/amd/display/dc/core/dc.c | 9 - drivers/gpu/drm/amd/display/dc/dcn10/Makefile | 2 +- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c | 365 --------------------- drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h | 277 ---------------- .../gpu/drm/amd/display/dc/dcn10/dcn10_resource.c | 57 ---- drivers/gpu/drm/amd/display/dc/inc/core_types.h | 3 - drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h | 193 ----------- 7 files changed, 1 insertion(+), 905 deletions(-) delete mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c delete mode 100644 drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h delete mode 100644 drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h diff --git a/drivers/gpu/drm/amd/display/dc/core/dc.c b/drivers/gpu/drm/amd/display/dc/core/dc.c index d86d9796e4cc..7fd42fc8bdfa 100644 --- a/drivers/gpu/drm/amd/display/dc/core/dc.c +++ b/drivers/gpu/drm/amd/display/dc/core/dc.c @@ -1525,15 +1525,6 @@ struct dc_link *dc_get_link_at_index(struct dc *dc, uint32_t link_index) return dc->links[link_index]; } -struct dwbc *dc_get_dwb_at_pipe(struct dc *dc, uint32_t pipe) -{ - if ((pipe >= dwb_pipe0) && (pipe < dwb_pipe_max_num)) { - return dc->res_pool->dwbc[(int)pipe]; - } else { - return NULL; - } -} - const struct graphics_object_id dc_get_link_id_at_index( struct dc *dc, uint32_t link_index) { diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile index e92ac2997a1a..2d6d3a371858 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/Makefile +++ b/drivers/gpu/drm/amd/display/dc/dcn10/Makefile @@ -3,7 +3,7 @@ DCN10 = dcn10_resource.o dcn10_ipp.o dcn10_hw_sequencer.o \ dcn10_dpp.o dcn10_opp.o dcn10_timing_generator.o \ - dcn10_mem_input.o dcn10_mpc.o dcn10_dwb.o \ + dcn10_mem_input.o dcn10_mpc.o \ dcn10_dpp_dscl.o dcn10_dpp_cm.o dcn10_dpp_cm_helper.o AMD_DAL_DCN10 = $(addprefix $(AMDDALPATH)/dc/dcn10/,$(DCN10)) diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c deleted file mode 100644 index 4ec5554f0f5b..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.c +++ /dev/null @@ -1,365 +0,0 @@ -/* - * Copyright 2012-17 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) - -#include "reg_helper.h" -#include "resource.h" -#include "dwb.h" -#include "dcn10_dwb.h" - - -#define REG(reg)\ - dwbc10->dwbc_regs->reg - -#define CTX \ - dwbc10->base.ctx - -#undef FN -#define FN(reg_name, field_name) \ - dwbc10->dwbc_shift->field_name, dwbc10->dwbc_mask->field_name - -#define TO_DCN10_DWBC(dwbc_base) \ - container_of(dwbc_base, struct dcn10_dwbc, base) - -static bool get_caps(struct dwbc *dwbc, struct dwb_caps *caps) -{ - if (caps) { - caps->adapter_id = 0; /* we only support 1 adapter currently */ - caps->hw_version = DCN_VERSION_1_0; - caps->num_pipes = 2; - memset(&caps->reserved, 0, sizeof(caps->reserved)); - memset(&caps->reserved2, 0, sizeof(caps->reserved2)); - caps->sw_version = dwb_ver_1_0; - caps->caps.support_dwb = true; - caps->caps.support_ogam = false; - caps->caps.support_wbscl = true; - caps->caps.support_ocsc = false; - return true; - } else { - return false; - } -} - -static bool enable(struct dwbc *dwbc) -{ - struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc); - - /* disable first. */ - dwbc->funcs->disable(dwbc); - - /* disable power gating */ - REG_UPDATE_5(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, 1, - DISPCLK_G_WB_GATE_DIS, 1, DISPCLK_G_WBSCL_GATE_DIS, 1, - WB_LB_LS_DIS, 1, WB_LUT_LS_DIS, 1); - - REG_UPDATE(WB_ENABLE, WB_ENABLE, 1); - - /* lock buffer0~buffer3 */ - REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, 0xf); - - /* buffer address for packing mode or Luma in planar mode */ - REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, (dwbc->config.basic_settings.luma_address[0] & 0xffffffff)); -/* REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, (dwbc->config.basic_settings.luma_address[0] >> 32)); */ - /* right eye sub-buffer address offset for packing mode or Luma in planar mode */ - REG_UPDATE(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB_BUF_1_ADDR_Y_OFFSET, 0); - - /* buffer address for Chroma in planar mode (unused in packing mode) */ - REG_UPDATE(MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, (dwbc->config.basic_settings.chroma_address[0] & 0xffffffff)); -/* REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, (dwbc->config.basic_settings.chroma_address[0] >> 32)); */ - /* right eye offset for packing mode or Luma in planar mode */ - REG_UPDATE(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB_BUF_1_ADDR_C_OFFSET, 0); - - /* buffer address for packing mode or Luma in planar mode */ - REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, (dwbc->config.basic_settings.luma_address[1] & 0xffffffff)); -/* REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, (dwbc->config.basic_settings.luma_address[1] >> 32)); */ - /* right eye sub-buffer address offset for packing mode or Luma in planar mode */ - REG_UPDATE(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB_BUF_2_ADDR_Y_OFFSET, 0); - - /* buffer address for Chroma in planar mode (unused in packing mode) */ - REG_UPDATE(MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, (dwbc->config.basic_settings.chroma_address[1] & 0xffffffff)); -/* REG_UPDATE(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, (dwbc->config.basic_settings.chroma_address[1] >> 32)); */ - /* right eye offset for packing mode or Luma in planar mode */ - REG_UPDATE(MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB_BUF_2_ADDR_C_OFFSET, 0); - - /* buffer address for packing mode or Luma in planar mode */ - REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, (dwbc->config.basic_settings.luma_address[2] & 0xffffffff)); -/* REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB_BUF_3_ADDR_Y_HIGH, (dwbc->config.basic_settings.luma_address[2] >> 32)); */ - /* right eye sub-buffer address offset for packing mode or Luma in planar mode */ - REG_UPDATE(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB_BUF_3_ADDR_Y_OFFSET, 0); - - /* buffer address for Chroma in planar mode (unused in packing mode) */ - REG_UPDATE(MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, (dwbc->config.basic_settings.chroma_address[2] & 0xffffffff)); -/* REG_UPDATE(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB_BUF_3_ADDR_C_HIGH, (dwbc->config.basic_settings.chroma_address[2] >> 32)); */ - /* right eye offset for packing mode or Luma in planar mode */ - REG_UPDATE(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB_BUF_3_ADDR_C_OFFSET, 0); - - /* buffer address for packing mode or Luma in planar mode */ - REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, (dwbc->config.basic_settings.luma_address[3] & 0xffffffff)); -/* REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB_BUF_4_ADDR_Y_HIGH, (dwbc->config.basic_settings.luma_address[3] >> 32)); */ - /* right eye sub-buffer address offset for packing mode or Luma in planar mode */ - REG_UPDATE(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB_BUF_4_ADDR_Y_OFFSET, 0); - - /* buffer address for Chroma in planar mode (unused in packing mode) */ - REG_UPDATE(MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, (dwbc->config.basic_settings.chroma_address[3] & 0xffffffff)); -/* REG_UPDATE(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB_BUF_4_ADDR_C_HIGH, (dwbc->config.basic_settings.chroma_address[3] >> 32)); */ - /* right eye offset for packing mode or Luma in planar mode */ - REG_UPDATE(MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB_BUF_4_ADDR_C_OFFSET, 0); - - /* setup luma & chroma size */ - REG_UPDATE(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, dwbc->config.basic_settings.luma_pitch * dwbc->config.basic_settings.dest_height); /* should be enough to contain a whole frame Luma data, same for stereo mode */ - REG_UPDATE(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, dwbc->config.basic_settings.chroma_pitch * dwbc->config.basic_settings.dest_height); /* should be enough to contain a whole frame Luma data, same for stereo mode */ - - /* enable address fence */ - REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, 1); - - /* setup pitch */ - REG_UPDATE_2(MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, dwbc->config.basic_settings.luma_pitch, - MCIF_WB_BUF_CHROMA_PITCH, dwbc->config.basic_settings.chroma_pitch); - - /* Set pitch for MC cache warm up mode */ - /* Pitch is 256 bytes aligned. The default pitch is 4K */ - REG_UPDATE(MCIF_WB_WARM_UP_CNTL, MCIF_WB_PITCH_SIZE_WARMUP, 0x10); /* default is 0x10 */ - - /* Programmed by the video driver based on the CRTC timing (for DWB) */ - REG_UPDATE(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, 0); - - /* Programming dwb watermark */ - /* Watermark to generate urgent in MCIF_WB_CLI, value is determined by MCIF_WB_CLI_WATERMARK_MASK. */ - /* Program in ns. A formula will be provided in the pseudo code to calculate the value. */ - REG_UPDATE(MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, 0x0); - REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, 0xffff); /* urgent_watermarkA */ - REG_UPDATE(MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, 0x1); - REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, 0xffff); /* urgent_watermarkB */ - REG_UPDATE(MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, 0x2); - REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, 0xffff); /* urgent_watermarkC */ - REG_UPDATE(MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, 0x3); - REG_UPDATE(MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, 0xffff); /* urgent_watermarkD */ - - /* Programming nb pstate watermark */ - REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x0); - REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_REFRESH_WATERMARK, 0xffff); /* nbp_state_change_watermarkA */ - REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x1); - REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_REFRESH_WATERMARK, 0xffff); /* nbp_state_change_watermarkB */ - REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x2); - REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_REFRESH_WATERMARK, 0xffff); /* nbp_state_change_watermarkC */ - REG_UPDATE(MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, 0x3); - REG_UPDATE(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_REFRESH_WATERMARK, 0xffff); /* nbp_state_change_watermarkD */ - - /* buf_lh_capability = (buffer_size / byte_per_pixel)*time_per_pixel; //client buffer latency hiding capability */ - /* if (MCIF_WB_CLI_WATERMARK * 2 < buf_lh_capability) //factor '2' can be adjusted if better value is identified during bringup/debug */ - /* MULTI_LEVEL_QOS_CTRL.MAX_SCALED_TIME_TO_URGENT = MCIF_WB_CLI_WATERMARK * 2; */ - /* else */ - /* MULTI_LEVEL_QOS_CTRL.MAX_SCALED_TIME_TO_URGENT = buf_lh_capability; //ensure QoS can be fully mapped to [0:15] region in any scenario */ - - REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, 31); - - /* Set arbitration unit for Luma/Chroma */ - /* arb_unit=2 should be chosen for more efficiency */ - REG_UPDATE(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, 2); /* Arbitration size, 0: 512 bytes 1: 1024 bytes 2: 2048 Bytes */ - - /* Program VMID, don't support virtual mode, won't set VMID */ - /* REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, pVmid); */ - - if (dwbc->config.basic_settings.input_pipe_select == dwb_pipe0) { - REG_UPDATE(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, dwbc->config.basic_settings.input_src_select - dwb_src_otg0); - } else if (dwbc->config.basic_settings.input_pipe_select == dwb_pipe1) { - REG_UPDATE(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, dwbc->config.basic_settings.input_src_select - dwb_src_otg0); - } - - /* Set interrupt mask */ - REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, 0); /* Disable interrupt to SW. (the default value is 0.) */ - REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, 0); /* Disable slice complete interrupt to SW.(the default value is 0.) */ - REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, 0); /* Disable frame buffer overrun interrupt to SW. (the default value is 0.) */ - - REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN, 1); /* Enable interrupt to VCE */ - REG_UPDATE(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, 0); /* Disable slice complete interrupt to VCE. */ - - /* ////////////////// */ - /* Enable Mcifwb */ - REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, 1); /* Start working */ - - /* unlock sw lock. */ - REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, 0); - - dwbc->status.enabled = true; - - return true; -} - -static bool disable(struct dwbc *dwbc) -{ - struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc); - - /* disable CNV */ - REG_UPDATE(CNV_MODE, CNV_FRAME_CAPTURE_EN, 0); - - /* disable WB */ - REG_UPDATE(WB_ENABLE, WB_ENABLE, 0); - - /* soft reset */ - REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 1); - REG_UPDATE(WB_SOFT_RESET, WB_SOFT_RESET, 0); - - /* enable power gating */ - REG_UPDATE_5(WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, 0, - DISPCLK_G_WB_GATE_DIS, 0, DISPCLK_G_WBSCL_GATE_DIS, 0, - WB_LB_LS_DIS, 0, WB_LUT_LS_DIS, 0); - - /* disable buffer manager */ - REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, 0); - - dwbc->status.enabled = false; - - return true; -} - -static bool get_status(struct dwbc *dwbc, struct dwb_status *status) -{ - if (status) { - memcpy(status, &dwbc->status, sizeof(struct dwb_status)); - return true; - } else { - return false; - } -} - -static bool dump_frame(struct dwbc *dwbc, struct dwb_frame_info *frame_info, - unsigned char *luma_buffer, unsigned char *chroma_buffer, - unsigned char *dest_luma_buffer, unsigned char *dest_chroma_buffer) -{ - struct dcn10_dwbc *dwbc10 = TO_DCN10_DWBC(dwbc); - - REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, 0xf); - - memcpy(dest_luma_buffer, luma_buffer, dwbc->config.basic_settings.luma_pitch * dwbc->config.basic_settings.dest_height); - memcpy(dest_chroma_buffer, chroma_buffer, dwbc->config.basic_settings.chroma_pitch * dwbc->config.basic_settings.dest_height / 2); - - REG_UPDATE(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, 0x0); - - frame_info->format = dwbc->config.advanced_settings.out_format; - frame_info->width = dwbc->config.basic_settings.dest_width; - frame_info->height = dwbc->config.basic_settings.dest_height; - frame_info->luma_pitch = dwbc->config.basic_settings.luma_pitch; - frame_info->chroma_pitch = dwbc->config.basic_settings.chroma_pitch; - frame_info->size = dwbc->config.basic_settings.dest_height * (dwbc->config.basic_settings.luma_pitch + dwbc->config.basic_settings.chroma_pitch); - - return true; -} - -static bool set_basic_settings(struct dwbc *dwbc, - const struct dwb_basic_settings *basic_settings) -{ - if (basic_settings) { - memcpy(&dwbc->config.basic_settings, basic_settings, sizeof(struct dwb_basic_settings)); - return true; - } else { - return false; - } -} - -static bool get_basic_settings(struct dwbc *dwbc, - struct dwb_basic_settings *basic_settings) -{ - if (basic_settings) { - memcpy(basic_settings, &dwbc->config.basic_settings, sizeof(struct dwb_basic_settings)); - return true; - } else { - return false; - } -} - -static bool set_advanced_settings(struct dwbc *dwbc, - const struct dwb_advanced_settings *advanced_settings) -{ - if (advanced_settings) { - if (advanced_settings->uFlag & sf_output_format) { - dwbc->config.advanced_settings.uFlag |= sf_output_format; - dwbc->config.advanced_settings.out_format = advanced_settings->out_format; - } - - if (advanced_settings->uFlag & sf_capture_rate) { - dwbc->config.advanced_settings.uFlag |= sf_capture_rate; - dwbc->config.advanced_settings.capture_rate = advanced_settings->capture_rate; - } - - return true; - } else { - return false; - } -} - -static bool get_advanced_settings(struct dwbc *dwbc, - struct dwb_advanced_settings *advanced_settings) -{ - if (advanced_settings) { - memcpy(advanced_settings, &dwbc->config.advanced_settings, sizeof(struct dwb_advanced_settings)); - return true; - } else { - return false; - } -} - -static bool reset_advanced_settings(struct dwbc *dwbc) -{ - dwbc->config.advanced_settings.uFlag = 0; - dwbc->config.advanced_settings.out_format = dwb_scaler_mode_bypass444; - dwbc->config.advanced_settings.capture_rate = dwb_capture_rate_0; - - return true; -} - -const struct dwbc_funcs dcn10_dwbc_funcs = { - .get_caps = get_caps, - .enable = enable, - .disable = disable, - .get_status = get_status, - .dump_frame = dump_frame, - .set_basic_settings = set_basic_settings, - .get_basic_settings = get_basic_settings, - .set_advanced_settings = set_advanced_settings, - .get_advanced_settings = get_advanced_settings, - .reset_advanced_settings = reset_advanced_settings, -}; - -void dcn10_dwbc_construct(struct dcn10_dwbc *dwbc10, - struct dc_context *ctx, - const struct dcn10_dwbc_registers *dwbc_regs, - const struct dcn10_dwbc_shift *dwbc_shift, - const struct dcn10_dwbc_mask *dwbc_mask, - int inst) -{ - dwbc10->base.ctx = ctx; - - dwbc10->base.inst = inst; - dwbc10->base.funcs = &dcn10_dwbc_funcs; - - dwbc10->dwbc_regs = dwbc_regs; - dwbc10->dwbc_shift = dwbc_shift; - dwbc10->dwbc_mask = dwbc_mask; -} - - -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h deleted file mode 100644 index 1fdc2be42fa9..000000000000 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_dwb.h +++ /dev/null @@ -1,277 +0,0 @@ -/* Copyright 2012-17 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ -#ifndef __DC_DWBC_DCN10_H__ -#define __DC_DWBC_DCN10_H__ - -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) - -/* DCN */ -#define BASE_INNER(seg) \ - DCE_BASE__INST0_SEG ## seg - -#define BASE(seg) \ - BASE_INNER(seg) - -#define SR(reg_name)\ - .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ - mm ## reg_name - -#define SRI(reg_name, block, id)\ - .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ - mm ## block ## id ## _ ## reg_name - - -#define SRII(reg_name, block, id)\ - .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ - mm ## block ## id ## _ ## reg_name - -#define SF(reg_name, field_name, post_fix)\ - .field_name = reg_name ## __ ## field_name ## post_fix - - -#define DWBC_COMMON_REG_LIST_DCN1_0(inst) \ - SRI(WB_ENABLE, CNV, inst),\ - SRI(WB_EC_CONFIG, CNV, inst),\ - SRI(CNV_MODE, CNV, inst),\ - SRI(WB_SOFT_RESET, CNV, inst),\ - SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\ - SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\ - SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB, inst),\ - SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\ - SRI(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MCIF_WB, inst),\ - SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\ - SRI(MCIF_WB_WATERMARK, MCIF_WB, inst),\ - SRI(MCIF_WB_WARM_UP_CNTL, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\ - SRI(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst),\ - .DWB_SOURCE_SELECT = mmDWB_SOURCE_SELECT\ - -#define DWBC_COMMON_MASK_SH_LIST_DCN1_0(mask_sh) \ - SF(CNV0_WB_ENABLE, WB_ENABLE, mask_sh),\ - SF(CNV0_WB_EC_CONFIG, DISPCLK_R_WB_GATE_DIS, mask_sh),\ - SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WB_GATE_DIS, mask_sh),\ - SF(CNV0_WB_EC_CONFIG, DISPCLK_G_WBSCL_GATE_DIS, mask_sh),\ - SF(CNV0_WB_EC_CONFIG, WB_LB_LS_DIS, mask_sh),\ - SF(CNV0_WB_EC_CONFIG, WB_LUT_LS_DIS, mask_sh),\ - SF(CNV0_CNV_MODE, CNV_WINDOW_CROP_EN, mask_sh),\ - SF(CNV0_CNV_MODE, CNV_STEREO_TYPE, mask_sh),\ - SF(CNV0_CNV_MODE, CNV_INTERLACED_MODE, mask_sh),\ - SF(CNV0_CNV_MODE, CNV_EYE_SELECTION, mask_sh),\ - SF(CNV0_CNV_MODE, CNV_STEREO_POLARITY, mask_sh),\ - SF(CNV0_CNV_MODE, CNV_INTERLACED_FIELD_ORDER, mask_sh),\ - SF(CNV0_CNV_MODE, CNV_STEREO_SPLIT, mask_sh),\ - SF(CNV0_CNV_MODE, CNV_NEW_CONTENT, mask_sh),\ - SF(CNV0_CNV_MODE, CNV_FRAME_CAPTURE_EN, mask_sh),\ - SF(CNV0_WB_SOFT_RESET, WB_SOFT_RESET, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_DUALSIZE_REQ, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_CHROMA_PITCH, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, WM_CHANGE_ACK_FORCE_ON, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB_BUF_1_ADDR_Y_OFFSET, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB_BUF_1_ADDR_C_OFFSET, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB_BUF_2_ADDR_Y_OFFSET, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB_BUF_2_ADDR_C_OFFSET, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB_BUF_3_ADDR_Y_OFFSET, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB_BUF_3_ADDR_C_OFFSET, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB_BUF_4_ADDR_Y_OFFSET, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB_BUF_4_ADDR_C_OFFSET, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK_IGNORE, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_ACK, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_REFRESH_WATERMARK, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_FORCE_ON, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_ALLOW_FOR_URGENT, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_WARM_UP_CNTL, MCIF_WB_PITCH_SIZE_WARMUP, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, mask_sh),\ - SF(MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, mask_sh),\ - SF(DWB_SOURCE_SELECT, OPTC_DWB0_SOURCE_SELECT, mask_sh),\ - SF(DWB_SOURCE_SELECT, OPTC_DWB1_SOURCE_SELECT, mask_sh) - -#define DWBC_REG_FIELD_LIST(type) \ - type WB_ENABLE;\ - type DISPCLK_R_WB_GATE_DIS;\ - type DISPCLK_G_WB_GATE_DIS;\ - type DISPCLK_G_WBSCL_GATE_DIS;\ - type WB_LB_LS_DIS;\ - type WB_LB_SD_DIS;\ - type WB_LUT_LS_DIS;\ - type CNV_WINDOW_CROP_EN;\ - type CNV_STEREO_TYPE;\ - type CNV_INTERLACED_MODE;\ - type CNV_EYE_SELECTION;\ - type CNV_STEREO_POLARITY;\ - type CNV_INTERLACED_FIELD_ORDER;\ - type CNV_STEREO_SPLIT;\ - type CNV_NEW_CONTENT;\ - type CNV_FRAME_CAPTURE_EN;\ - type WB_SOFT_RESET;\ - type MCIF_WB_BUFMGR_ENABLE;\ - type MCIF_WB_BUF_DUALSIZE_REQ;\ - type MCIF_WB_BUFMGR_SW_INT_EN;\ - type MCIF_WB_BUFMGR_SW_INT_ACK;\ - type MCIF_WB_BUFMGR_SW_SLICE_INT_EN;\ - type MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN;\ - type MCIF_WB_BUFMGR_SW_LOCK;\ - type MCIF_WB_P_VMID;\ - type MCIF_WB_BUF_ADDR_FENCE_EN;\ - type MCIF_WB_BUF_LUMA_PITCH;\ - type MCIF_WB_BUF_CHROMA_PITCH;\ - type MCIF_WB_CLIENT_ARBITRATION_SLICE;\ - type MCIF_WB_TIME_PER_PIXEL;\ - type WM_CHANGE_ACK_FORCE_ON;\ - type MCIF_WB_CLI_WATERMARK_MASK;\ - type MCIF_WB_BUF_1_ADDR_Y;\ - type MCIF_WB_BUF_1_ADDR_Y_OFFSET;\ - type MCIF_WB_BUF_1_ADDR_C;\ - type MCIF_WB_BUF_1_ADDR_C_OFFSET;\ - type MCIF_WB_BUF_2_ADDR_Y;\ - type MCIF_WB_BUF_2_ADDR_Y_OFFSET;\ - type MCIF_WB_BUF_2_ADDR_C;\ - type MCIF_WB_BUF_2_ADDR_C_OFFSET;\ - type MCIF_WB_BUF_3_ADDR_Y;\ - type MCIF_WB_BUF_3_ADDR_Y_OFFSET;\ - type MCIF_WB_BUF_3_ADDR_C;\ - type MCIF_WB_BUF_3_ADDR_C_OFFSET;\ - type MCIF_WB_BUF_4_ADDR_Y;\ - type MCIF_WB_BUF_4_ADDR_Y_OFFSET;\ - type MCIF_WB_BUF_4_ADDR_C;\ - type MCIF_WB_BUF_4_ADDR_C_OFFSET;\ - type MCIF_WB_BUFMGR_VCE_LOCK_IGNORE;\ - type MCIF_WB_BUFMGR_VCE_INT_EN;\ - type MCIF_WB_BUFMGR_VCE_INT_ACK;\ - type MCIF_WB_BUFMGR_VCE_SLICE_INT_EN;\ - type MCIF_WB_BUFMGR_VCE_LOCK;\ - type MCIF_WB_BUFMGR_SLICE_SIZE;\ - type NB_PSTATE_CHANGE_REFRESH_WATERMARK;\ - type NB_PSTATE_CHANGE_URGENT_DURING_REQUEST;\ - type NB_PSTATE_CHANGE_FORCE_ON;\ - type NB_PSTATE_ALLOW_FOR_URGENT;\ - type NB_PSTATE_CHANGE_WATERMARK_MASK;\ - type MCIF_WB_CLI_WATERMARK;\ - type MCIF_WB_CLI_CLOCK_GATER_OVERRIDE;\ - type MCIF_WB_PITCH_SIZE_WARMUP;\ - type MCIF_WB_BUF_LUMA_SIZE;\ - type MCIF_WB_BUF_CHROMA_SIZE;\ - type OPTC_DWB0_SOURCE_SELECT;\ - type OPTC_DWB1_SOURCE_SELECT;\ - -struct dcn10_dwbc_registers { - uint32_t WB_ENABLE; - uint32_t WB_EC_CONFIG; - uint32_t CNV_MODE; - uint32_t WB_SOFT_RESET; - uint32_t MCIF_WB_BUFMGR_SW_CONTROL; - uint32_t MCIF_WB_BUF_PITCH; - uint32_t MCIF_WB_ARBITRATION_CONTROL; - uint32_t MCIF_WB_SCLK_CHANGE; - uint32_t MCIF_WB_BUF_1_ADDR_Y; - uint32_t MCIF_WB_BUF_1_ADDR_Y_OFFSET; - uint32_t MCIF_WB_BUF_1_ADDR_C; - uint32_t MCIF_WB_BUF_1_ADDR_C_OFFSET; - uint32_t MCIF_WB_BUF_2_ADDR_Y; - uint32_t MCIF_WB_BUF_2_ADDR_Y_OFFSET; - uint32_t MCIF_WB_BUF_2_ADDR_C; - uint32_t MCIF_WB_BUF_2_ADDR_C_OFFSET; - uint32_t MCIF_WB_BUF_3_ADDR_Y; - uint32_t MCIF_WB_BUF_3_ADDR_Y_OFFSET; - uint32_t MCIF_WB_BUF_3_ADDR_C; - uint32_t MCIF_WB_BUF_3_ADDR_C_OFFSET; - uint32_t MCIF_WB_BUF_4_ADDR_Y; - uint32_t MCIF_WB_BUF_4_ADDR_Y_OFFSET; - uint32_t MCIF_WB_BUF_4_ADDR_C; - uint32_t MCIF_WB_BUF_4_ADDR_C_OFFSET; - uint32_t MCIF_WB_BUFMGR_VCE_CONTROL; - uint32_t MCIF_WB_NB_PSTATE_LATENCY_WATERMARK; - uint32_t MCIF_WB_NB_PSTATE_CONTROL; - uint32_t MCIF_WB_WATERMARK; - uint32_t MCIF_WB_WARM_UP_CNTL; - uint32_t MCIF_WB_BUF_LUMA_SIZE; - uint32_t MCIF_WB_BUF_CHROMA_SIZE; - uint32_t DWB_SOURCE_SELECT; -}; -struct dcn10_dwbc_mask { - DWBC_REG_FIELD_LIST(uint32_t) -}; -struct dcn10_dwbc_shift { - DWBC_REG_FIELD_LIST(uint8_t) -}; -struct dcn10_dwbc { - struct dwbc base; - const struct dcn10_dwbc_registers *dwbc_regs; - const struct dcn10_dwbc_shift *dwbc_shift; - const struct dcn10_dwbc_mask *dwbc_mask; -}; - -void dcn10_dwbc_construct(struct dcn10_dwbc *dwbc10, - struct dc_context *ctx, - const struct dcn10_dwbc_registers *dwbc_regs, - const struct dcn10_dwbc_shift *dwbc_shift, - const struct dcn10_dwbc_mask *dwbc_mask, - int inst); - -#endif - -#endif diff --git a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c index 71adda0e5b59..e21ba8c2f8d4 100644 --- a/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c +++ b/drivers/gpu/drm/amd/display/dc/dcn10/dcn10_resource.c @@ -32,7 +32,6 @@ #include "dcn10/dcn10_ipp.h" #include "dcn10/dcn10_mpc.h" -#include "dcn10/dcn10_dwb.h" #include "irq/dcn10/irq_service_dcn10.h" #include "dcn10/dcn10_dpp.h" #include "dcn10/dcn10_timing_generator.h" @@ -326,24 +325,6 @@ static const struct dcn_dpp_mask tf_mask = { TF_REG_LIST_SH_MASK_DCN10(_MASK), }; -#define dwbc_regs(id)\ -[id] = {\ - DWBC_COMMON_REG_LIST_DCN1_0(id),\ -} - -static const struct dcn10_dwbc_registers dwbc10_regs[] = { - dwbc_regs(0), - dwbc_regs(1), -}; - -static const struct dcn10_dwbc_shift dwbc10_shift = { - DWBC_COMMON_MASK_SH_LIST_DCN1_0(__SHIFT) -}; - -static const struct dcn10_dwbc_mask dwbc10_mask = { - DWBC_COMMON_MASK_SH_LIST_DCN1_0(_MASK) -}; - static const struct dcn_mpc_registers mpc_regs = { MPC_COMMON_REG_LIST_DCN1_0(0), MPC_COMMON_REG_LIST_DCN1_0(1), @@ -430,7 +411,6 @@ static const struct resource_caps res_cap = { .num_audio = 4, .num_stream_encoder = 4, .num_pll = 4, - .num_dwb = 2, }; static const struct dc_debug debug_defaults_drv = { @@ -767,11 +747,6 @@ static void destruct(struct dcn10_resource_pool *pool) dce_aud_destroy(&pool->base.audios[i]); } - for (i = 0; i < pool->base.res_cap->num_dwb; i++) { - kfree(pool->base.dwbc[i]); - pool->base.dwbc[i] = NULL; - } - for (i = 0; i < pool->base.clk_src_count; i++) { if (pool->base.clock_sources[i] != NULL) { dcn10_clock_source_destroy(&pool->base.clock_sources[i]); @@ -1234,31 +1209,6 @@ static uint32_t read_pipe_fuses(struct dc_context *ctx) return value; } -static bool dcn10_dwbc_create(struct dc_context *ctx, struct resource_pool *pool) -{ - int i; - uint32_t dwb_count = pool->res_cap->num_dwb; - - for (i = 0; i < dwb_count; i++) { - struct dcn10_dwbc *dwbc10 = kzalloc(sizeof(struct dcn10_dwbc), - GFP_KERNEL); - - if (!dwbc10) { - dm_error("DC: failed to create dwbc10!\n"); - return false; - } - - dcn10_dwbc_construct(dwbc10, ctx, - &dwbc10_regs[i], - &dwbc10_shift, - &dwbc10_mask, - i); - - pool->dwbc[i] = &dwbc10->base; - } - return true; -} - static bool construct( uint8_t num_virtual_links, struct dc *dc, @@ -1479,12 +1429,6 @@ static bool construct( goto mpc_create_fail; } -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) - if (!dcn10_dwbc_create(ctx, &pool->base)) { - goto dwbc_create_fail; - } -#endif - if (!resource_construct(num_virtual_links, dc, &pool->base, (!IS_FPGA_MAXIMUS_DC(dc->ctx->dce_environment) ? &res_create_funcs : &res_create_maximus_funcs))) @@ -1507,7 +1451,6 @@ static bool construct( irqs_create_fail: res_create_fail: clock_source_create_fail: -dwbc_create_fail: destruct(pool); diff --git a/drivers/gpu/drm/amd/display/dc/inc/core_types.h b/drivers/gpu/drm/amd/display/dc/inc/core_types.h index 915d5c10361b..1a1d322da8cc 100644 --- a/drivers/gpu/drm/amd/display/dc/inc/core_types.h +++ b/drivers/gpu/drm/amd/display/dc/inc/core_types.h @@ -35,7 +35,6 @@ #if defined(CONFIG_DRM_AMD_DC_DCN1_0) #include "mpc.h" #endif -#include "dwb.h" #define MAX_CLOCK_SOURCES 7 @@ -136,8 +135,6 @@ struct resource_pool { struct pp_smu_funcs_rv *pp_smu; struct pp_smu_display_requirement_rv pp_smu_req; - struct dwbc *dwbc[MAX_DWB_PIPES]; - unsigned int pipe_count; unsigned int underlay_pipe_index; unsigned int stream_enc_count; diff --git a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h b/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h deleted file mode 100644 index 82347ba480fe..000000000000 --- a/drivers/gpu/drm/amd/display/dc/inc/hw/dwb.h +++ /dev/null @@ -1,193 +0,0 @@ -/* Copyright 2012-17 Advanced Micro Devices, Inc. - * - * Permission is hereby granted, free of charge, to any person obtaining a - * copy of this software and associated documentation files (the "Software"), - * to deal in the Software without restriction, including without limitation - * the rights to use, copy, modify, merge, publish, distribute, sublicense, - * and/or sell copies of the Software, and to permit persons to whom the - * Software is furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR - * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, - * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR - * OTHER DEALINGS IN THE SOFTWARE. - * - * Authors: AMD - * - */ - -#ifndef __DC_DWBC_H__ -#define __DC_DWBC_H__ - -#include "dc_hw_types.h" - -#define MAX_DWB_PIPES 3 - -enum dce_version; - -enum dwb_sw_version { - dwb_ver_1_0 = 1, -}; - -enum dwb_source { - dwb_src_scl = 0, /* for DCE7x/9x, DCN won't support. */ - dwb_src_blnd, /* for DCE7x/9x */ - dwb_src_fmt, /* for DCE7x/9x */ -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) - dwb_src_otg0 = 0x100, /* for DCN1.x, register: mmDWB_SOURCE_SELECT */ - dwb_src_otg1, /* for DCN1.x */ - dwb_src_otg2, /* for DCN1.x */ - dwb_src_otg3, /* for DCN1.x */ -#endif -}; - -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) -/* DCN1.x supports 2 pipes */ -#endif -enum dwb_pipe { - dwb_pipe0 = 0, -#if defined(CONFIG_DRM_AMD_DC_DCN1_0) - dwb_pipe1, -#endif - dwb_pipe_max_num, -}; - -enum setting_flags { - sf_pipe = 0x00000001, - sf_output_format = 0x00000002, - sf_capture_rate = 0x00000004, - sf_all = 0xffffffff, -}; - -enum dwb_capture_rate { - - dwb_capture_rate_0 = 0, /* Every frame is captured. */ - dwb_capture_rate_1 = 1, /* Every other frame is captured. */ - dwb_capture_rate_2 = 2, /* Every 3rd frame is captured. */ - dwb_capture_rate_3 = 3, /* Every 4th frame is captured. */ -}; - -enum dwb_scaler_mode { - dwb_scaler_mode_bypass444 = 0, - dwb_scaler_mode_rgb444 = 1, - dwb_scaler_mode_yuv444 = 2, - dwb_scaler_mode_yuv420 = 3 -}; - -struct dwb_caps { - enum dce_version hw_version; /* DCN engine version. */ - enum dwb_sw_version sw_version; /* DWB sw implementation version. */ - unsigned int reserved[6]; /* Reserved for future use, MUST BE 0. */ - unsigned int adapter_id; - unsigned int num_pipes; /* number of DWB pipes */ - struct { - unsigned int support_dwb :1; - unsigned int support_ogam :1; - unsigned int support_wbscl :1; - unsigned int support_ocsc :1; - } caps; - unsigned int reserved2[10]; /* Reserved for future use, MUST BE 0. */ -}; - -struct dwb_status { - bool enabled; - /* Reserved ========================================================================= */ - unsigned int reserved[8]; /* Reserved fields */ -}; - -struct dwb_basic_settings { - /* General DWB related input parameters ============================================= */ - enum dwb_source input_src_select; /* Select input source: (DCE) 0: SCL; 1: BLND; 2: FMT; (DCN) OTG* or MPC* */ - enum dwb_pipe input_pipe_select; /* Select input pipe: 0: PIPE0; 1: PIPE1; 2: PIPE2 */ - - /* CNV: WND Related parameters ====================================================== */ - unsigned int capture_rate; /* Captures once every (capture_rate+1) frames */ - - /* CNV: CSC Related parameters ====================================================== */ - unsigned int start_x; /* Horizontal window start position */ - unsigned int start_y; /* Vertical window start position */ - unsigned int src_width; /* Width of window captured within source window */ - unsigned int src_height; /* Height of window captured within source window */ - - /* SISCL Related parameters ========================================================= */ - unsigned int dest_width; /* Destination width */ - unsigned int dest_height; /* Destination height */ - - /* MCIF bufer parameters ========================================================= */ - unsigned long long luma_address[4]; - unsigned long long chroma_address[4]; - unsigned int luma_pitch; - unsigned int chroma_pitch; - unsigned int slice_lines; - - /* Reserved ========================================================================= */ - unsigned int reserved[8]; /* Reserved fields */ - -}; - -struct dwb_advanced_settings { - enum setting_flags uFlag; - enum dwb_pipe pipe; /* default = DWB_PIPE_ALL */ - enum dwb_scaler_mode out_format; /* default = DWBScalerMode_YUV420 */ - enum dwb_capture_rate capture_rate; /* default = Every frame is captured */ - unsigned int reserved[64]; /* reserved for future use, must be 0 */ -}; - -/* / - dwb_frame_info is the info of the dumping data */ -struct dwb_frame_info { - unsigned int size; - unsigned int width; - unsigned int height; - unsigned int luma_pitch; - unsigned int chroma_pitch; - enum dwb_scaler_mode format; -}; - -struct dwbc_cfg { - struct dwb_basic_settings basic_settings; - struct dwb_advanced_settings advanced_settings; -}; - -struct dwbc { - const struct dwbc_funcs *funcs; - struct dc_context *ctx; - struct dwbc_cfg config; - struct dwb_status status; - int inst; -}; - -struct dwbc_funcs { - bool (*get_caps)(struct dwbc *dwbc, struct dwb_caps *caps); - - bool (*enable)(struct dwbc *dwbc); - - bool (*disable)(struct dwbc *dwbc); - - bool (*get_status)(struct dwbc *dwbc, struct dwb_status *status); - - bool (*dump_frame)(struct dwbc *dwbc, struct dwb_frame_info *frame_info, - unsigned char *luma_buffer, unsigned char *chroma_buffer, - unsigned char *dest_luma_buffer, unsigned char *dest_chroma_buffer); - - bool (*set_basic_settings)(struct dwbc *dwbc, - const struct dwb_basic_settings *basic_settings); - - bool (*get_basic_settings)(struct dwbc *dwbc, - struct dwb_basic_settings *basic_settings); - - bool (*set_advanced_settings)(struct dwbc *dwbc, - const struct dwb_advanced_settings *advanced_settings); - - bool (*get_advanced_settings)(struct dwbc *dwbc, - struct dwb_advanced_settings *advanced_settings); - - bool (*reset_advanced_settings)(struct dwbc *dwbc); -}; - -#endif