From patchwork Mon Jan 15 22:06:54 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Lyude Paul X-Patchwork-Id: 10165407 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D84BD60325 for ; Mon, 15 Jan 2018 22:09:40 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id CA41A2624D for ; Mon, 15 Jan 2018 22:09:40 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id BEE1126E46; Mon, 15 Jan 2018 22:09:40 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.2 required=2.0 tests=BAYES_00, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 4C8452624D for ; Mon, 15 Jan 2018 22:09:40 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 769D989D4F; Mon, 15 Jan 2018 22:09:39 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mx1.redhat.com (mx1.redhat.com [209.132.183.28]) by gabe.freedesktop.org (Postfix) with ESMTPS id 2C33689D4F; Mon, 15 Jan 2018 22:09:38 +0000 (UTC) Received: from smtp.corp.redhat.com (int-mx04.intmail.prod.int.phx2.redhat.com [10.5.11.14]) (using TLSv1.2 with cipher AECDH-AES256-SHA (256/256 bits)) (No client certificate requested) by mx1.redhat.com (Postfix) with ESMTPS id 840A21A407A; Mon, 15 Jan 2018 22:09:37 +0000 (UTC) Received: from malachite.bss.redhat.com (dhcp-10-20-1-30.bss.redhat.com [10.20.1.30]) by smtp.corp.redhat.com (Postfix) with ESMTP id D1E4F5D962; Mon, 15 Jan 2018 22:09:30 +0000 (UTC) From: Lyude Paul To: nouveau@lists.freedesktop.org Subject: [RFC 4/4] drm/nouveau: Add SLCG clockgating for Kepler2 Date: Mon, 15 Jan 2018 17:06:54 -0500 Message-Id: <20180115220755.16780-5-lyude@redhat.com> In-Reply-To: <20180115220755.16780-1-lyude@redhat.com> References: <20180115220755.16780-1-lyude@redhat.com> X-Scanned-By: MIMEDefang 2.79 on 10.5.11.14 X-Greylist: Sender IP whitelisted, not delayed by milter-greylist-4.5.16 (mx1.redhat.com [10.5.110.39]); Mon, 15 Jan 2018 22:09:37 +0000 (UTC) Cc: David Airlie , Greg Kroah-Hartman , Karol Herbst , dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org, Ben Skeggs , Thomas Gleixner , Rhys Kidd X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.18 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP That's right, there's still more power saving to go! This enables the third level of clockgating, SLCG (this stands for... we don't actually know what this stands for yet :\). While the register values look a little different, programming them is exactly the same as BLCG. Additionally, it should be noted that SLCG was added starting with kepler2, previous generations have no SLCG. SLCG can be enabled with the nouveau config option, NvPmEnableGating=3 Signed-off-by: Lyude Paul --- .../gpu/drm/nouveau/include/nvkm/subdev/therm.h | 1 + drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c | 108 +++++++++++++++++++++ drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c | 3 +- 3 files changed, 111 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h b/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h index 4b49561415ef..ba50207791e0 100644 --- a/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h +++ b/drivers/gpu/drm/nouveau/include/nvkm/subdev/therm.h @@ -50,6 +50,7 @@ enum nvkm_therm_clkgate_level { NVKM_THERM_CLKGATE_NONE = 0, NVKM_THERM_CLKGATE_CG, /* basic clockgating */ NVKM_THERM_CLKGATE_BLCG, + NVKM_THERM_CLKGATE_SLCG, }; struct nvkm_therm_clkgate_init { diff --git a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c index d26bfa3062e6..35ad52529c9a 100644 --- a/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c +++ b/drivers/gpu/drm/nouveau/nvkm/engine/gr/gk110.c @@ -187,6 +187,89 @@ gk110_clkgate_blcg_init_gpc_mp_0[] = { {} }; +const struct nvkm_therm_clkgate_init +gk110_clkgate_slcg_init_main_0[] = { + { 0x4041f4, 1, 0x00000000 }, + { 0x409894, 1, 0x00000000 }, + {} +}; + +const struct nvkm_therm_clkgate_init +gk110_clkgate_slcg_init_unk_0[] = { + { 0x406004, 1, 0x00000000 }, + {} +}; + +const struct nvkm_therm_clkgate_init +gk110_clkgate_slcg_init_sked_0[] = { + { 0x407004, 1, 0x00000000 }, + {} +}; + +const struct nvkm_therm_clkgate_init +gk110_clkgate_slcg_init_gpc_ctxctl_0[] = { + { 0x41a894, 1, 0x00000000 }, + {} +}; + +const struct nvkm_therm_clkgate_init +gk110_clkgate_slcg_init_gpc_unk_0[] = { + { 0x418504, 1, 0x00000000 }, + { 0x41860c, 1, 0x00000000 }, + { 0x41868c, 1, 0x00000000 }, + {} +}; + +const struct nvkm_therm_clkgate_init +gk110_clkgate_slcg_init_gpc_esetup_0[] = { + { 0x41882c, 1, 0x00000000 }, + {} +}; + +const struct nvkm_therm_clkgate_init +gk110_clkgate_slcg_init_gpc_zcull_0[] = { + { 0x418974, 1, 0x00000000 }, + {} +}; + +const struct nvkm_therm_clkgate_init +gk110_clkgate_slcg_init_gpc_l1c_0[] = { + { 0x419cd8, 2, 0x00000000 }, + {} +}; + +const struct nvkm_therm_clkgate_init +gk110_clkgate_slcg_init_gpc_unk_1[] = { + { 0x419c74, 1, 0x00000000 }, + {} +}; + +const struct nvkm_therm_clkgate_init +gk110_clkgate_slcg_init_gpc_mp_0[] = { + { 0x419fd4, 1, 0x00004a4a }, + { 0x419fdc, 1, 0x00000014 }, + { 0x419fe4, 1, 0x00000000 }, + { 0x419ff4, 1, 0x00001724 }, + {} +}; + +const struct nvkm_therm_clkgate_init +gk110_clkgate_slcg_init_gpc_ppc_0[] = { + { 0x41be2c, 1, 0x00000000 }, + {} +}; + +/* TODO: add ELPG here */ + +const struct nvkm_therm_clkgate_init +gk110_clkgate_slcg_init_pcounter_0[] = { + { 0x1be018, 1, 0x000001ff }, + { 0x1bc018, 1, 0x000001ff }, + { 0x1b8018, 1, 0x000001ff }, + { 0x1b4124, 1, 0x00000000 }, + {} +}; + const struct nvkm_therm_clkgate_pack gk110_clkgate_pack[] = { { @@ -220,6 +303,31 @@ gk110_clkgate_pack[] = { NULL, }, }, + { + NVKM_THERM_CLKGATE_SLCG, + (const struct nvkm_therm_clkgate_init*[]) { + gk110_clkgate_slcg_init_main_0, + gk110_clkgate_slcg_init_unk_0, + gk110_clkgate_slcg_init_sked_0, + gk110_clkgate_slcg_init_gpc_ctxctl_0, + gk110_clkgate_slcg_init_gpc_unk_0, + gk110_clkgate_slcg_init_gpc_esetup_0, + gk110_clkgate_slcg_init_gpc_zcull_0, + gk110_clkgate_slcg_init_gpc_l1c_0, + gk110_clkgate_slcg_init_gpc_unk_1, + gk110_clkgate_slcg_init_gpc_mp_0, + gk110_clkgate_slcg_init_gpc_ppc_0, + NULL, + }, + }, + /* TODO: ELPG programming happens -here- */ + { + NVKM_THERM_CLKGATE_SLCG, + (const struct nvkm_therm_clkgate_init*[]) { + gk110_clkgate_slcg_init_pcounter_0, + NULL + }, + }, {} }; diff --git a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c index ee028d099f6a..587dcc7444a7 100644 --- a/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c +++ b/drivers/gpu/drm/nouveau/nvkm/subdev/therm/base.c @@ -332,6 +332,7 @@ nvkm_therm_clkgate_oneinit(struct nvkm_therm *therm) switch (therm->clkgate_level) { case NVKM_THERM_CLKGATE_CG: clkgate_str = "CG"; break; case NVKM_THERM_CLKGATE_BLCG: clkgate_str = "BLCG"; break; + case NVKM_THERM_CLKGATE_SLCG: clkgate_str = "SLCG"; break; default: BUG(); } @@ -449,7 +450,7 @@ nvkm_therm_ctor(struct nvkm_therm *therm, struct nvkm_device *device, clamp((int)nvkm_longopt(device->cfgopt, "NvPmEnableGating", NVKM_THERM_CLKGATE_NONE), - NVKM_THERM_CLKGATE_NONE, NVKM_THERM_CLKGATE_BLCG); + NVKM_THERM_CLKGATE_NONE, NVKM_THERM_CLKGATE_SLCG); } int