From patchwork Wed Jan 24 02:56:03 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Gurchetan Singh X-Patchwork-Id: 10181309 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id C1C9860467 for ; Wed, 24 Jan 2018 02:56:31 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id B5776285BA for ; Wed, 24 Jan 2018 02:56:31 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id A91FF28631; Wed, 24 Jan 2018 02:56:31 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.1 required=2.0 tests=BAYES_00,DKIM_SIGNED, RCVD_IN_DNSWL_MED,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 30B00285BA for ; Wed, 24 Jan 2018 02:56:30 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 149716E4F2; Wed, 24 Jan 2018 02:56:30 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-pf0-x244.google.com (mail-pf0-x244.google.com [IPv6:2607:f8b0:400e:c00::244]) by gabe.freedesktop.org (Postfix) with ESMTPS id 56AEC6E4F2 for ; Wed, 24 Jan 2018 02:56:28 +0000 (UTC) Received: by mail-pf0-x244.google.com with SMTP id a88so1934498pfe.12 for ; Tue, 23 Jan 2018 18:56:28 -0800 (PST) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=chromium.org; s=google; h=from:to:cc:subject:date:message-id; bh=cYF5guU3RXmagk5g3jGrtShiotIZ4pn9pHatC7TWQu8=; b=O0b7ltkbwBVxS04YXSp36hsTHz2eysWsVqSpU5uIgPkDbIPZWtpBgqA4/nr+W4UkAM oPtdcOiQpS4mCoHX5Es/dH1mbR/PleGwANsgKV6jWsK03xZP6d+qtVLwNzVj2qlNANw4 x7v3a2d/GjhaorpFMib2J5EuqY0IdgeKjRlTM= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id; bh=cYF5guU3RXmagk5g3jGrtShiotIZ4pn9pHatC7TWQu8=; b=Z8MUL+OTaH7QcFyqlkH4O2DFWWXWLcnocKOYb9EGCB3K/jKpVh7b8oQLmV+TZbDptK DAbSyGT7GhbF/TnlawsAS3kRTy5geN1ONXt1t0PtIAe2UvM6FiTGG4OhfXJ3rif+73HV OzGjoNc8xbzQFeBgNx+yEIk8m9rWI6SLhzZmukX/NdcqkZ3HwhTUEnYDCklr/3PpeNPi R19eryT//dUGf3GW78jdMvrh1YwSSRYww4fL5b4ckorI43vNg4mSL0pMLTmbrmGB/uK0 RYBiER7y7NpnrFgi+SEX29QAKyna5Dnmahcd4NIoAQ3F73wR3f8iLNwb/fYeA3t+rAsf f+ow== X-Gm-Message-State: AKwxyteEJlYDofnKCmHp+M+LWS8k/LOOsvPBElwJDiCJjWAdRMgYCLDM DR2gi2F29vKtIlFZMfQC/JMScV4MOoE= X-Google-Smtp-Source: AH8x2241YB+d62mUxeDBoqgjZcJWRyEezLAFPTlDY2DNo3I5IHa7RV5BsVqSp4plHllIoyTSPfsSPw== X-Received: by 10.101.96.78 with SMTP id b14mr9939455pgv.339.1516762587502; Tue, 23 Jan 2018 18:56:27 -0800 (PST) Received: from gurchetansingh0.mtv.corp.google.com ([2620:0:1000:1600:f560:c8e6:9f8d:ba54]) by smtp.gmail.com with ESMTPSA id i20sm7041301pfj.58.2018.01.23.18.56.26 (version=TLS1_2 cipher=ECDHE-RSA-AES128-SHA bits=128/128); Tue, 23 Jan 2018 18:56:26 -0800 (PST) From: Gurchetan Singh To: dri-devel@lists.freedesktop.org Subject: [PATCH 2/5] drm: add ARM flush implementation Date: Tue, 23 Jan 2018 18:56:03 -0800 Message-Id: <20180124025606.3020-2-gurchetansingh@chromium.org> X-Mailer: git-send-email 2.13.5 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Gurchetan Singh , thierry.reding@gmail.com, laurent.pinchart@ideasonboard.com, daniel.vetter@intel.com, linux-arm-kernel@lists.infradead.org MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP The dma_cache_maint_page function is important for cache maintenance on ARM32 (this was determined via testing). Since we desire direct control of the caches in drm_cache.c, let's make a copy of the function, rename it and use it. v2: Don't use DMA API, call functions directly (Daniel) Signed-off-by: Gurchetan Singh --- drivers/gpu/drm/drm_cache.c | 61 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 61 insertions(+) diff --git a/drivers/gpu/drm/drm_cache.c b/drivers/gpu/drm/drm_cache.c index 89cdd32fe1f3..5124582451c6 100644 --- a/drivers/gpu/drm/drm_cache.c +++ b/drivers/gpu/drm/drm_cache.c @@ -69,6 +69,55 @@ static void drm_cache_flush_clflush(struct page *pages[], } #endif +#if defined(CONFIG_ARM) +static void drm_cache_maint_page(struct page *page, unsigned long offset, + size_t size, enum dma_data_direction dir, + void (*op)(const void *, size_t, int)) +{ + unsigned long pfn; + size_t left = size; + + pfn = page_to_pfn(page) + offset / PAGE_SIZE; + offset %= PAGE_SIZE; + + /* + * A single sg entry may refer to multiple physically contiguous + * pages. But we still need to process highmem pages individually. + * If highmem is not configured then the bulk of this loop gets + * optimized out. + */ + do { + size_t len = left; + void *vaddr; + + page = pfn_to_page(pfn); + + if (PageHighMem(page)) { + if (len + offset > PAGE_SIZE) + len = PAGE_SIZE - offset; + + if (cache_is_vipt_nonaliasing()) { + vaddr = kmap_atomic(page); + op(vaddr + offset, len, dir); + kunmap_atomic(vaddr); + } else { + vaddr = kmap_high_get(page); + if (vaddr) { + op(vaddr + offset, len, dir); + kunmap_high(page); + } + } + } else { + vaddr = page_address(page) + offset; + op(vaddr, len, dir); + } + offset = 0; + pfn++; + left -= len; + } while (left); +} +#endif + /** * drm_flush_pages - Flush dcache lines of a set of pages. * @pages: List of pages to be flushed. @@ -104,6 +153,12 @@ drm_flush_pages(struct page *pages[], unsigned long num_pages) (unsigned long)page_virtual + PAGE_SIZE); kunmap_atomic(page_virtual); } +#elif defined(CONFIG_ARM) + unsigned long i; + + for (i = 0; i < num_pages; i++) + drm_cache_maint_page(pages[i], 0, PAGE_SIZE, DMA_TO_DEVICE, + dmac_map_area); #else pr_err("Architecture has no drm_cache.c support\n"); WARN_ON_ONCE(1); @@ -135,6 +190,12 @@ drm_flush_sg(struct sg_table *st) if (wbinvd_on_all_cpus()) pr_err("Timed out waiting for cache flush\n"); +#elif defined(CONFIG_ARM) + struct sg_page_iter sg_iter; + + for_each_sg_page(st->sgl, &sg_iter, st->nents, 0) + drm_cache_maint_page(sg_page_iter_page(&sg_iter), 0, PAGE_SIZE, + DMA_TO_DEVICE, dmac_map_area); #else pr_err("Architecture has no drm_cache.c support\n"); WARN_ON_ONCE(1);