From patchwork Tue Apr 24 07:48:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Maxime Ripard X-Patchwork-Id: 10358851 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id D19F9601BE for ; Tue, 24 Apr 2018 07:48:20 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id C6A0E28D1F for ; Tue, 24 Apr 2018 07:48:20 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id B99A128D26; Tue, 24 Apr 2018 07:48:20 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 280E928D1F for ; Tue, 24 Apr 2018 07:48:20 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 2BAA96E38A; Tue, 24 Apr 2018 07:48:18 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail.bootlin.com (mail.bootlin.com [62.4.15.54]) by gabe.freedesktop.org (Postfix) with ESMTP id 520686E38A for ; Tue, 24 Apr 2018 07:48:16 +0000 (UTC) Received: by mail.bootlin.com (Postfix, from userid 110) id 628472070D; Tue, 24 Apr 2018 09:48:15 +0200 (CEST) Received: from localhost (LStLambert-657-1-97-87.w90-63.abo.wanadoo.fr [90.63.216.87]) by mail.bootlin.com (Postfix) with ESMTPSA id 36FA02038E; Tue, 24 Apr 2018 09:48:15 +0200 (CEST) From: Maxime Ripard To: Eric Anholt Subject: [PATCH] drm/vc4: plane: Expand the lower bits using the LSB Date: Tue, 24 Apr 2018 09:48:14 +0200 Message-Id: <20180424074814.6922-1-maxime.ripard@bootlin.com> X-Mailer: git-send-email 2.17.0 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Maxime Ripard , dri-devel@lists.freedesktop.org MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP The vc4 HVS uses an internal RGB888 representation of the frames, and will by default expand formats using a lower depth using zeros. This causes an issue when we try to use other compositing software such as pixman that seems to be filling the missing bits using the format least significant bit value. As such, this prevents us from checking the display output in a reliable way. To prevent this, force the same behaviour so that we can do such things. Signed-off-by: Maxime Ripard --- drivers/gpu/drm/vc4/vc4_plane.c | 1 + drivers/gpu/drm/vc4/vc4_regs.h | 8 ++++++++ 2 files changed, 9 insertions(+) diff --git a/drivers/gpu/drm/vc4/vc4_plane.c b/drivers/gpu/drm/vc4/vc4_plane.c index ce39390be389..8dd33c6e9fd8 100644 --- a/drivers/gpu/drm/vc4/vc4_plane.c +++ b/drivers/gpu/drm/vc4/vc4_plane.c @@ -542,6 +542,7 @@ static int vc4_plane_mode_set(struct drm_plane *plane, /* Control word */ vc4_dlist_write(vc4_state, SCALER_CTL0_VALID | + VC4_SET_FIELD(SCALER_CTL0_EXPAND_LSB, SCALER_CTL0_EXPAND) | (format->pixel_order << SCALER_CTL0_ORDER_SHIFT) | (format->hvs << SCALER_CTL0_PIXEL_FORMAT_SHIFT) | VC4_SET_FIELD(tiling, SCALER_CTL0_TILING) | diff --git a/drivers/gpu/drm/vc4/vc4_regs.h b/drivers/gpu/drm/vc4/vc4_regs.h index a141496104a6..7c28e6207ec2 100644 --- a/drivers/gpu/drm/vc4/vc4_regs.h +++ b/drivers/gpu/drm/vc4/vc4_regs.h @@ -806,12 +806,20 @@ enum hvs_pixel_format { #define SCALER_CTL0_ORDER_MASK VC4_MASK(14, 13) #define SCALER_CTL0_ORDER_SHIFT 13 +#define SCALER_CTL0_EXPAND_MASK VC4_MASK(12, 11) +#define SCALER_CTL0_EXPAND_SHIFT 11 + #define SCALER_CTL0_SCL1_MASK VC4_MASK(10, 8) #define SCALER_CTL0_SCL1_SHIFT 8 #define SCALER_CTL0_SCL0_MASK VC4_MASK(7, 5) #define SCALER_CTL0_SCL0_SHIFT 5 +#define SCALER_CTL0_EXPAND_ZERO 0 +#define SCALER_CTL0_EXPAND_LSB 1 +#define SCALER_CTL0_EXPAND_MSB 2 +#define SCALER_CTL0_EXPAND_REPEAT 3 + #define SCALER_CTL0_SCL_H_PPF_V_PPF 0 #define SCALER_CTL0_SCL_H_TPZ_V_PPF 1 #define SCALER_CTL0_SCL_H_PPF_V_TPZ 2