From patchwork Fri May 18 09:45:14 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Jagan Teki X-Patchwork-Id: 10414113 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id ECB3D6032B for ; Mon, 21 May 2018 08:20:38 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id DF06428450 for ; Mon, 21 May 2018 08:20:38 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id D3773287AE; Mon, 21 May 2018 08:20:38 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-2.8 required=2.0 tests=BAYES_00,DKIM_SIGNED, MAILING_LIST_MULTI,T_DKIM_INVALID autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id A1D3F28450 for ; Mon, 21 May 2018 08:20:18 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 956836E330; Mon, 21 May 2018 08:18:19 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-pf0-x244.google.com (mail-pf0-x244.google.com [IPv6:2607:f8b0:400e:c00::244]) by gabe.freedesktop.org (Postfix) with ESMTPS id 931F56ECD7 for ; Fri, 18 May 2018 09:46:25 +0000 (UTC) Received: by mail-pf0-x244.google.com with SMTP id j20-v6so3501356pff.10 for ; Fri, 18 May 2018 02:46:25 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=amarulasolutions.com; s=google; h=from:to:cc:subject:date:message-id:in-reply-to:references; bh=Ff220eub+m7pYVmfvVeX+umdxthxaMATGIZlH/KsC4I=; b=TV1p2dXlIyCSjwi6TDlM4JDUoJFY16ZyeJgaQivAFzo+VFn44NCbShLbFwdOtnz/9o Qenmjxljyg9ftjgTinzHWtNdMRFdbsvfupsj7m6dHyunkOPZLPQ+Mg8e16p8wZOIsG8I SD/V2TgFKNrvov32QzFCmIWyPqvS2iO8gpK4k= X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=Ff220eub+m7pYVmfvVeX+umdxthxaMATGIZlH/KsC4I=; b=gN0wMEYO6VaG0RcsuG5U6CGe4wfEg9vVPTOfYdoXMHB/Wq3ABUlp70vjBo/fYInFMg 3J7VNIehJSQEpT9fJihNr2/ShW55kGvEjcVDDtb/RCdedflF4j5ksStlzBZYFIjjPGgC 7WUAz+SXqVjITES26jhjxGb4tPGRONnsog/CCtMA6nDIyNdAhJPdmKcfI3Snhd3E9dCm 2POxZK0Y3nRRgwalO2UW086UnkRhXdL0VZ6BF/TMz6i3ggEVzha473onCiDQo3/3PXYl auvtFtnCB4ujVgTHkXRi0ciyO3qlrHm3H8KN8RvOry9yPKN3GRRHQoII1DTE5Zf8hkuf a/Vw== X-Gm-Message-State: ALKqPweOLdpNPZmq4LSBBXscrQPSjZ0X9hy8SGX1RX0d9n4ycM2Ex+Im G6ReqtLi68eRhuWWnzQjC1lksQ== X-Google-Smtp-Source: AB8JxZovCzFOy5BtQGUR3nZ07Fexznz6sY/cCP1xbHxQzKYN4jr44upOgA5eaFWY5N4EyL5lYPMReQ== X-Received: by 2002:a62:98cb:: with SMTP id d72-v6mr8649536pfk.98.1526636785110; Fri, 18 May 2018 02:46:25 -0700 (PDT) Received: from localhost.localdomain ([183.82.227.74]) by smtp.gmail.com with ESMTPSA id j11-v6sm12694097pff.64.2018.05.18.02.46.17 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Fri, 18 May 2018 02:46:24 -0700 (PDT) From: Jagan Teki To: Maxime Ripard , Chen-Yu Tsai , Icenowy Zheng , Jernej Skrabec , Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , David Airlie , dri-devel@lists.freedesktop.org, Michael Turquette , Stephen Boyd , linux-clk@vger.kernel.org, Michael Trimarchi , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-sunxi@googlegroups.com Subject: [PATCH v2 04/26] clk: sunxi-ng: a64: Add minimal rate for video PLLs Date: Fri, 18 May 2018 15:15:14 +0530 Message-Id: <20180518094536.17201-5-jagan@amarulasolutions.com> X-Mailer: git-send-email 2.14.3 In-Reply-To: <20180518094536.17201-1-jagan@amarulasolutions.com> References: <20180518094536.17201-1-jagan@amarulasolutions.com> X-Mailman-Approved-At: Mon, 21 May 2018 08:18:09 +0000 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Jagan Teki MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP According to documentation and experience with other similar SoCs, video PLLs don't work stable if their output frequency is set below 192 MHz. Because of that, set minimal rate to both A64 video PLLs to 192 MHz. Signed-off-by: Jagan Teki --- Changes for v2: - New patch drivers/clk/sunxi-ng/ccu-sun50i-a64.c | 46 ++++++++++++++++++----------------- 1 file changed, 24 insertions(+), 22 deletions(-) diff --git a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c index ee9c12cf3f08..d0e30192f0cf 100644 --- a/drivers/clk/sunxi-ng/ccu-sun50i-a64.c +++ b/drivers/clk/sunxi-ng/ccu-sun50i-a64.c @@ -64,17 +64,18 @@ static SUNXI_CCU_NM_WITH_GATE_LOCK(pll_audio_base_clk, "pll-audio-base", BIT(28), /* lock */ CLK_SET_RATE_UNGATE); -static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video0_clk, "pll-video0", - "osc24M", 0x010, - 8, 7, /* N */ - 0, 4, /* M */ - BIT(24), /* frac enable */ - BIT(25), /* frac select */ - 270000000, /* frac rate 0 */ - 297000000, /* frac rate 1 */ - BIT(31), /* gate */ - BIT(28), /* lock */ - CLK_SET_RATE_UNGATE); +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video0_clk, "pll-video0", + "osc24M", 0x010, + 192000000, /* Minimum rate */ + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_ve_clk, "pll-ve", "osc24M", 0x018, @@ -125,17 +126,18 @@ static struct ccu_nk pll_periph1_clk = { }, }; -static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_video1_clk, "pll-video1", - "osc24M", 0x030, - 8, 7, /* N */ - 0, 4, /* M */ - BIT(24), /* frac enable */ - BIT(25), /* frac select */ - 270000000, /* frac rate 0 */ - 297000000, /* frac rate 1 */ - BIT(31), /* gate */ - BIT(28), /* lock */ - CLK_SET_RATE_UNGATE); +static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK_MIN(pll_video1_clk, "pll-video1", + "osc24M", 0x030, + 192000000, /* Minimum rate */ + 8, 7, /* N */ + 0, 4, /* M */ + BIT(24), /* frac enable */ + BIT(25), /* frac select */ + 270000000, /* frac rate 0 */ + 297000000, /* frac rate 1 */ + BIT(31), /* gate */ + BIT(28), /* lock */ + CLK_SET_RATE_UNGATE); static SUNXI_CCU_NM_WITH_FRAC_GATE_LOCK(pll_gpu_clk, "pll-gpu", "osc24M", 0x038,