From 7b3b4cae2b0283076b47775efdf5dbbf75a8d859 Mon Sep 17 00:00:00 2001
From: Lowry Li <lowry.li@arm.com>
Date: Mon, 28 May 2018 18:27:33 +0800
Subject: [PATCH v2 2/2] drm/mali-dp: Implement plane alpha and pixel blend on
malidp
Check the pixel blending mode and plane alpha value when
do the plane_check. Mali DP supports blending the current plane
with the background either based on the pixel alpha blending
mode or by using the layer's alpha value, but not both at the
same time. If both case, plane_check will return failed.
Set the HW when doing plane_update accordingly. If plane alpha
is the 0xffff, set the PREM bit accordingly. If not we'd set
ALPHA bit as zero and layer alpha value.
Signed-off-by: Lowry Li <lowry.li@arm.com>
---
drivers/gpu/drm/arm/malidp_planes.c | 65 ++++++++++++++++++++++++++-----------
1 file changed, 46 insertions(+), 19 deletions(-)
@@ -31,6 +31,7 @@
#define LAYER_COMP_MASK (0x3 << 12)
#define LAYER_COMP_PIXEL (0x3 << 12)
#define LAYER_COMP_PLANE (0x2 << 12)
+#define LAYER_PMUL_ENABLE (0x1 << 14)
#define MALIDP_LAYER_COMPOSE 0x008
#define MALIDP_LAYER_SIZE 0x00c
#define LAYER_H_VAL(x) (((x) & 0x1fff) << 0)
@@ -110,6 +111,7 @@ static int malidp_de_plane_check(struct drm_plane *plane,
struct drm_rect clip = { 0 };
int i, ret;
u32 src_w, src_h;
+ u16 pixel_alpha = state->pixel_blend_mode;
if (!state->crtc || !state->fb)
return 0;
@@ -178,6 +180,11 @@ static int malidp_de_plane_check(struct drm_plane *plane,
ms->rotmem_size = val;
}
+ /* HW can't support plane + pixel blending */
+ if ((state->alpha != DRM_BLEND_ALPHA_OPAQUE) &&
+ (pixel_alpha != DRM_MODE_BLEND_PIXEL_NONE))
+ return -EINVAL;
+
return 0;
}
@@ -206,7 +213,11 @@ static void malidp_de_plane_update(struct drm_plane *plane,
struct drm_gem_cma_object *obj;
struct malidp_plane *mp;
const struct malidp_hw_regmap *map;
- struct malidp_plane_state *ms = to_malidp_plane_state(plane->state);
+ struct drm_plane_state *state = plane->state;
+ struct malidp_plane_state *ms = to_malidp_plane_state(state);
+ u16 pixel_alpha = state->pixel_blend_mode;
+ u8 plane_alpha = state->alpha >> 8;
+ u8 alpha_bits = state->fb->format->alpha;
u16 ptr;
u32 src_w, src_h, dest_w, dest_h, val;
int i;
@@ -215,10 +226,10 @@ static void malidp_de_plane_update(struct drm_plane *plane,
map = &mp->hwdev->map;
/* convert src values from Q16 fixed point to integer */
- src_w = plane->state->src_w >> 16;
- src_h = plane->state->src_h >> 16;
- dest_w = plane->state->crtc_w;
- dest_h = plane->state->crtc_h;
+ src_w = state->src_w >> 16;
+ src_h = state->src_h >> 16;
+ dest_w = state->crtc_w;
+ dest_h = state->crtc_h;
malidp_hw_write(mp->hwdev, ms->format, mp->layer->base);
@@ -226,13 +237,13 @@ static void malidp_de_plane_update(struct drm_plane *plane,
/* calculate the offset for the layer's plane registers */
ptr = mp->layer->ptr + (i << 4);
- obj = drm_fb_cma_get_gem_obj(plane->state->fb, i);
+ obj = drm_fb_cma_get_gem_obj(state->fb, i);
obj->paddr += plane->state->fb->offsets[i];
malidp_hw_write(mp->hwdev, lower_32_bits(obj->paddr), ptr);
malidp_hw_write(mp->hwdev, upper_32_bits(obj->paddr), ptr + 4);
}
malidp_de_set_plane_pitches(mp, ms->n_planes,
- plane->state->fb->pitches);
+ state->fb->pitches);
malidp_hw_write(mp->hwdev, LAYER_H_VAL(src_w) | LAYER_V_VAL(src_h),
mp->layer->base + MALIDP_LAYER_SIZE);
@@ -240,8 +251,8 @@ static void malidp_de_plane_update(struct drm_plane *plane,
malidp_hw_write(mp->hwdev, LAYER_H_VAL(dest_w) | LAYER_V_VAL(dest_h),
mp->layer->base + MALIDP_LAYER_COMP_SIZE);
- malidp_hw_write(mp->hwdev, LAYER_H_VAL(plane->state->crtc_x) |
- LAYER_V_VAL(plane->state->crtc_y),
+ malidp_hw_write(mp->hwdev, LAYER_H_VAL(state->crtc_x) |
+ LAYER_V_VAL(state->crtc_y),
mp->layer->base + MALIDP_LAYER_OFFSET);
if (mp->layer->id == DE_SMART)
@@ -254,20 +265,30 @@ static void malidp_de_plane_update(struct drm_plane *plane,
val &= ~LAYER_ROT_MASK;
/* setup the rotation and axis flip bits */
- if (plane->state->rotation & DRM_ROTATE_MASK)
- val |= ilog2(plane->state->rotation & DRM_ROTATE_MASK) <<
+ if (state->rotation & DRM_ROTATE_MASK)
+ val |= ilog2(state->rotation & DRM_ROTATE_MASK) <<
LAYER_ROT_OFFSET;
- if (plane->state->rotation & DRM_REFLECT_X)
+ if (state->rotation & DRM_REFLECT_X)
val |= LAYER_H_FLIP;
- if (plane->state->rotation & DRM_REFLECT_Y)
+ if (state->rotation & DRM_REFLECT_Y)
val |= LAYER_V_FLIP;
- /*
- * always enable pixel alpha blending until we have a way to change
- * blend modes
- */
- val &= ~LAYER_COMP_MASK;
- val |= LAYER_COMP_PIXEL;
+ val &= ~(LAYER_COMP_MASK | LAYER_PMUL_ENABLE);
+
+ if (state->alpha != DRM_BLEND_ALPHA_OPAQUE) {
+ val |= LAYER_COMP_PLANE | LAYER_ALPHA(plane_alpha);
+ } else if (alpha_bits != 0) {
+ /* We only care about blend mode if the format has alpha */
+ switch (pixel_alpha) {
+ case DRM_MODE_BLEND_PREMULTI:
+ val |= LAYER_COMP_PIXEL | LAYER_PMUL_ENABLE;
+ break;
+ case DRM_MODE_BLEND_COVERAGE:
+ val |= LAYER_COMP_PIXEL;
+ break;
+ }
+ val |= LAYER_ALPHA(0xff);
+ }
/* set the 'enable layer' bit */
val |= LAYER_ENABLE;
@@ -300,6 +321,9 @@ int malidp_de_planes_init(struct drm_device *drm)
unsigned long crtcs = 1 << drm->mode_config.num_crtc;
unsigned long flags = DRM_ROTATE_0 | DRM_ROTATE_90 | DRM_ROTATE_180 |
DRM_ROTATE_270 | DRM_REFLECT_X | DRM_REFLECT_Y;
+ unsigned int blend_caps = BIT(DRM_MODE_BLEND_PIXEL_NONE) |
+ BIT(DRM_MODE_BLEND_PREMULTI) |
+ BIT(DRM_MODE_BLEND_COVERAGE);
u32 *formats;
int ret, i, j, n;
@@ -351,6 +375,9 @@ int malidp_de_planes_init(struct drm_device *drm)
drm_plane_create_rotation_property(&plane->base, DRM_ROTATE_0, flags);
malidp_hw_write(malidp->dev, MALIDP_ALPHA_LUT,
plane->layer->base + MALIDP_LAYER_COMPOSE);
+
+ drm_plane_create_alpha_property(&plane->base);
+ drm_plane_create_blend_mode_property(&plane->base, blend_caps);
}
kfree(formats);
--
1.9.1