From patchwork Mon Jun 25 21:06:05 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Alex Deucher X-Patchwork-Id: 10487271 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id 1E5D26038C for ; Mon, 25 Jun 2018 21:06:36 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id 0FFD0286A8 for ; Mon, 25 Jun 2018 21:06:36 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 04DA9286BD; Mon, 25 Jun 2018 21:06:36 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, DKIM_ADSP_CUSTOM_MED, FREEMAIL_FROM, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 7260B286A8 for ; Mon, 25 Jun 2018 21:06:35 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id A8DEB6E3C5; Mon, 25 Jun 2018 21:06:33 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from mail-qt0-x244.google.com (mail-qt0-x244.google.com [IPv6:2607:f8b0:400d:c0d::244]) by gabe.freedesktop.org (Postfix) with ESMTPS id CB98E6E3D2; Mon, 25 Jun 2018 21:06:22 +0000 (UTC) Received: by mail-qt0-x244.google.com with SMTP id c23-v6so4391867qtn.6; Mon, 25 Jun 2018 14:06:22 -0700 (PDT) X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20161025; h=x-gm-message-state:from:to:cc:subject:date:message-id:in-reply-to :references; bh=RmooZYqZPTPEcZwa03FpIRD+oGW9oLIZH0OjNYmotXA=; b=CAKcGShSWfakcyQICRePV1HAYmJq954p/SBqBwB9CdkC0OhOmyf8I7ka8YXDziu031 i1jUKts2gvcvp20O88X2xc+yODqB7SSMd/W2YzkzWhSwO/dqZEUHh1zl8MHsgR8RK1U5 4yumUjw91cpiF7ZzdGy1GSa4S6zJnbzlxLe6tePrwcNrJP6zOuf2dMcpmXli+hsAmerX kqNArgX0MP04vZ3Tnn9kRBBIK9UJ8jrS/VRDvIMbxafrLqz5bDJjwZLzekgn+jf4D1RV IsNXn/+J57hM+kEbZI7BoGEMz9+1TnVHegH23TqP5Zp01MNY2Fjt+fmPrJDvp+V926Zj 8qdQ== X-Gm-Message-State: APt69E3ogYqtZiWHas2OUTIoWxbe1qN4bcS5mjdEfeiOjI+qYiHypZF4 OXod9RNk0OcT2fYrH4zgaBZcfQ== X-Google-Smtp-Source: AAOMgpe5EcVzum8mz21Dhq6ek5iiciDds/t3AcjlOqzmjTM9c5RGbhpVSwe61B7wRd4D3JJdQdZdbg== X-Received: by 2002:aed:2457:: with SMTP id s23-v6mr4424083qtc.366.1529960781601; Mon, 25 Jun 2018 14:06:21 -0700 (PDT) Received: from localhost.localdomain ([76.1.164.143]) by smtp.gmail.com with ESMTPSA id q13-v6sm4016108qkl.97.2018.06.25.14.06.20 (version=TLS1_2 cipher=ECDHE-RSA-CHACHA20-POLY1305 bits=256/256); Mon, 25 Jun 2018 14:06:20 -0700 (PDT) From: Alex Deucher X-Google-Original-From: Alex Deucher To: amd-gfx@lists.freedesktop.org, dri-devel@lists.freedesktop.org, airlied@gmail.com, linux-pci@vger.kernel.org, bhelgaas@google.com Subject: [PATCH 4/5] drm/radeon: use pcie functions for link width Date: Mon, 25 Jun 2018 16:06:05 -0500 Message-Id: <20180625210606.2736-5-alexander.deucher@amd.com> X-Mailer: git-send-email 2.13.6 In-Reply-To: <20180625210606.2736-1-alexander.deucher@amd.com> References: <20180625210606.2736-1-alexander.deucher@amd.com> X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Alex Deucher MIME-Version: 1.0 Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP This is the last user of drm_pcie_get_speed_cap_mask. Use the pci version so we can drop drm_pcie_get_speed_cap_mask. Signed-off-by: Alex Deucher --- drivers/gpu/drm/radeon/ci_dpm.c | 20 +++++++++++++++----- drivers/gpu/drm/radeon/cik.c | 22 ++++++++++++---------- drivers/gpu/drm/radeon/r600_dpm.c | 4 ++-- drivers/gpu/drm/radeon/radeon.h | 4 ++++ drivers/gpu/drm/radeon/si.c | 22 ++++++++++++---------- drivers/gpu/drm/radeon/si_dpm.c | 20 +++++++++++++++----- 6 files changed, 60 insertions(+), 32 deletions(-) diff --git a/drivers/gpu/drm/radeon/ci_dpm.c b/drivers/gpu/drm/radeon/ci_dpm.c index b9302c918271..d587779a80b4 100644 --- a/drivers/gpu/drm/radeon/ci_dpm.c +++ b/drivers/gpu/drm/radeon/ci_dpm.c @@ -5676,19 +5676,29 @@ int ci_dpm_init(struct radeon_device *rdev) u16 data_offset, size; u8 frev, crev; struct ci_power_info *pi; + enum pci_bus_speed speed_cap; + struct pci_dev *root = rdev->pdev->bus->self; int ret; - u32 mask; pi = kzalloc(sizeof(struct ci_power_info), GFP_KERNEL); if (pi == NULL) return -ENOMEM; rdev->pm.dpm.priv = pi; - ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); - if (ret) + speed_cap = pcie_get_speed_cap(root); + if (speed_cap == PCI_SPEED_UNKNOWN) { pi->sys_pcie_mask = 0; - else - pi->sys_pcie_mask = mask; + } else { + if (speed_cap == PCIE_SPEED_8_0GT) + pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | + RADEON_PCIE_SPEED_50 | + RADEON_PCIE_SPEED_80; + else if (speed_cap == PCIE_SPEED_5_0GT) + pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | + RADEON_PCIE_SPEED_50; + else + pi->sys_pcie_mask = RADEON_PCIE_SPEED_25; + } pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; pi->pcie_gen_performance.max = RADEON_PCIE_GEN1; diff --git a/drivers/gpu/drm/radeon/cik.c b/drivers/gpu/drm/radeon/cik.c index 7c73bc7e2f85..ebce4601a305 100644 --- a/drivers/gpu/drm/radeon/cik.c +++ b/drivers/gpu/drm/radeon/cik.c @@ -9499,9 +9499,10 @@ int cik_set_vce_clocks(struct radeon_device *rdev, u32 evclk, u32 ecclk) static void cik_pcie_gen3_enable(struct radeon_device *rdev) { struct pci_dev *root = rdev->pdev->bus->self; + enum pci_bus_speed speed_cap; int bridge_pos, gpu_pos; - u32 speed_cntl, mask, current_data_rate; - int ret, i; + u32 speed_cntl, current_data_rate; + int i; u16 tmp16; if (pci_is_root_bus(rdev->pdev->bus)) @@ -9516,23 +9517,24 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) if (!(rdev->flags & RADEON_IS_PCIE)) return; - ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); - if (ret != 0) + speed_cap = pcie_get_speed_cap(root); + if (speed_cap == PCI_SPEED_UNKNOWN) return; - if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80))) + if ((speed_cap != PCIE_SPEED_8_0GT) && + (speed_cap != PCIE_SPEED_5_0GT)) return; speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >> LC_CURRENT_DATA_RATE_SHIFT; - if (mask & DRM_PCIE_SPEED_80) { + if (speed_cap == PCIE_SPEED_8_0GT) { if (current_data_rate == 2) { DRM_INFO("PCIE gen 3 link speeds already enabled\n"); return; } DRM_INFO("enabling PCIE gen 3 link speeds, disable with radeon.pcie_gen2=0\n"); - } else if (mask & DRM_PCIE_SPEED_50) { + } else if (speed_cap == PCIE_SPEED_5_0GT) { if (current_data_rate == 1) { DRM_INFO("PCIE gen 2 link speeds already enabled\n"); return; @@ -9548,7 +9550,7 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) if (!gpu_pos) return; - if (mask & DRM_PCIE_SPEED_80) { + if (speed_cap == PCIE_SPEED_8_0GT) { /* re-try equalization if gen3 is not already enabled */ if (current_data_rate != 2) { u16 bridge_cfg, gpu_cfg; @@ -9636,9 +9638,9 @@ static void cik_pcie_gen3_enable(struct radeon_device *rdev) pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); tmp16 &= ~0xf; - if (mask & DRM_PCIE_SPEED_80) + if (speed_cap == PCIE_SPEED_8_0GT) tmp16 |= 3; /* gen3 */ - else if (mask & DRM_PCIE_SPEED_50) + else if (speed_cap == PCIE_SPEED_5_0GT) tmp16 |= 2; /* gen2 */ else tmp16 |= 1; /* gen1 */ diff --git a/drivers/gpu/drm/radeon/r600_dpm.c b/drivers/gpu/drm/radeon/r600_dpm.c index 73d4c5348116..5e044c98fca2 100644 --- a/drivers/gpu/drm/radeon/r600_dpm.c +++ b/drivers/gpu/drm/radeon/r600_dpm.c @@ -1327,9 +1327,9 @@ enum radeon_pcie_gen r600_get_pcie_gen_support(struct radeon_device *rdev, case RADEON_PCIE_GEN3: return RADEON_PCIE_GEN3; default: - if ((sys_mask & DRM_PCIE_SPEED_80) && (default_gen == RADEON_PCIE_GEN3)) + if ((sys_mask & RADEON_PCIE_SPEED_80) && (default_gen == RADEON_PCIE_GEN3)) return RADEON_PCIE_GEN3; - else if ((sys_mask & DRM_PCIE_SPEED_50) && (default_gen == RADEON_PCIE_GEN2)) + else if ((sys_mask & RADEON_PCIE_SPEED_50) && (default_gen == RADEON_PCIE_GEN2)) return RADEON_PCIE_GEN2; else return RADEON_PCIE_GEN1; diff --git a/drivers/gpu/drm/radeon/radeon.h b/drivers/gpu/drm/radeon/radeon.h index 4a2eb409aacc..1a6f6edb3515 100644 --- a/drivers/gpu/drm/radeon/radeon.h +++ b/drivers/gpu/drm/radeon/radeon.h @@ -1653,6 +1653,10 @@ struct radeon_pm { struct radeon_dpm dpm; }; +#define RADEON_PCIE_SPEED_25 1 +#define RADEON_PCIE_SPEED_50 2 +#define RADEON_PCIE_SPEED_80 4 + int radeon_pm_get_type_index(struct radeon_device *rdev, enum radeon_pm_state_type ps_type, int instance); diff --git a/drivers/gpu/drm/radeon/si.c b/drivers/gpu/drm/radeon/si.c index 1907c950d76f..85c604d29235 100644 --- a/drivers/gpu/drm/radeon/si.c +++ b/drivers/gpu/drm/radeon/si.c @@ -7082,9 +7082,10 @@ int si_set_uvd_clocks(struct radeon_device *rdev, u32 vclk, u32 dclk) static void si_pcie_gen3_enable(struct radeon_device *rdev) { struct pci_dev *root = rdev->pdev->bus->self; + enum pci_bus_speed speed_cap; int bridge_pos, gpu_pos; - u32 speed_cntl, mask, current_data_rate; - int ret, i; + u32 speed_cntl, current_data_rate; + int i; u16 tmp16; if (pci_is_root_bus(rdev->pdev->bus)) @@ -7099,23 +7100,24 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) if (!(rdev->flags & RADEON_IS_PCIE)) return; - ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); - if (ret != 0) + speed_cap = pcie_get_speed_cap(root); + if (speed_cap == PCI_SPEED_UNKNOWN) return; - if (!(mask & (DRM_PCIE_SPEED_50 | DRM_PCIE_SPEED_80))) + if ((speed_cap != PCIE_SPEED_8_0GT) && + (speed_cap != PCIE_SPEED_5_0GT)) return; speed_cntl = RREG32_PCIE_PORT(PCIE_LC_SPEED_CNTL); current_data_rate = (speed_cntl & LC_CURRENT_DATA_RATE_MASK) >> LC_CURRENT_DATA_RATE_SHIFT; - if (mask & DRM_PCIE_SPEED_80) { + if (speed_cap == PCIE_SPEED_8_0GT) { if (current_data_rate == 2) { DRM_INFO("PCIE gen 3 link speeds already enabled\n"); return; } DRM_INFO("enabling PCIE gen 3 link speeds, disable with radeon.pcie_gen2=0\n"); - } else if (mask & DRM_PCIE_SPEED_50) { + } else if (speed_cap == PCIE_SPEED_5_0GT) { if (current_data_rate == 1) { DRM_INFO("PCIE gen 2 link speeds already enabled\n"); return; @@ -7131,7 +7133,7 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) if (!gpu_pos) return; - if (mask & DRM_PCIE_SPEED_80) { + if (speed_cap == PCIE_SPEED_8_0GT) { /* re-try equalization if gen3 is not already enabled */ if (current_data_rate != 2) { u16 bridge_cfg, gpu_cfg; @@ -7219,9 +7221,9 @@ static void si_pcie_gen3_enable(struct radeon_device *rdev) pci_read_config_word(rdev->pdev, gpu_pos + PCI_EXP_LNKCTL2, &tmp16); tmp16 &= ~0xf; - if (mask & DRM_PCIE_SPEED_80) + if (speed_cap == PCIE_SPEED_8_0GT) tmp16 |= 3; /* gen3 */ - else if (mask & DRM_PCIE_SPEED_50) + else if (speed_cap == PCIE_SPEED_5_0GT) tmp16 |= 2; /* gen2 */ else tmp16 |= 1; /* gen1 */ diff --git a/drivers/gpu/drm/radeon/si_dpm.c b/drivers/gpu/drm/radeon/si_dpm.c index fea88078cf8e..8fb60b3af015 100644 --- a/drivers/gpu/drm/radeon/si_dpm.c +++ b/drivers/gpu/drm/radeon/si_dpm.c @@ -6899,8 +6899,9 @@ int si_dpm_init(struct radeon_device *rdev) struct ni_power_info *ni_pi; struct si_power_info *si_pi; struct atom_clock_dividers dividers; + enum pci_bus_speed speed_cap; + struct pci_dev *root = rdev->pdev->bus->self; int ret; - u32 mask; si_pi = kzalloc(sizeof(struct si_power_info), GFP_KERNEL); if (si_pi == NULL) @@ -6910,11 +6911,20 @@ int si_dpm_init(struct radeon_device *rdev) eg_pi = &ni_pi->eg; pi = &eg_pi->rv7xx; - ret = drm_pcie_get_speed_cap_mask(rdev->ddev, &mask); - if (ret) + speed_cap = pcie_get_speed_cap(root); + if (speed_cap == PCI_SPEED_UNKNOWN) { si_pi->sys_pcie_mask = 0; - else - si_pi->sys_pcie_mask = mask; + } else { + if (speed_cap == PCIE_SPEED_8_0GT) + si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | + RADEON_PCIE_SPEED_50 | + RADEON_PCIE_SPEED_80; + else if (speed_cap == PCIE_SPEED_5_0GT) + si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25 | + RADEON_PCIE_SPEED_50; + else + si_pi->sys_pcie_mask = RADEON_PCIE_SPEED_25; + } si_pi->force_pcie_gen = RADEON_PCIE_GEN_INVALID; si_pi->boot_pcie_gen = si_get_current_pcie_speed(rdev);