From patchwork Fri Jun 29 17:02:47 2018 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: 7bit X-Patchwork-Submitter: Benoit Parrot X-Patchwork-Id: 10497115 Return-Path: Received: from mail.wl.linuxfoundation.org (pdx-wl-mail.web.codeaurora.org [172.30.200.125]) by pdx-korg-patchwork.web.codeaurora.org (Postfix) with ESMTP id B6537601C7 for ; Fri, 29 Jun 2018 17:26:49 +0000 (UTC) Received: from mail.wl.linuxfoundation.org (localhost [127.0.0.1]) by mail.wl.linuxfoundation.org (Postfix) with ESMTP id A452A29635 for ; Fri, 29 Jun 2018 17:26:49 +0000 (UTC) Received: by mail.wl.linuxfoundation.org (Postfix, from userid 486) id 9827829645; Fri, 29 Jun 2018 17:26:49 +0000 (UTC) X-Spam-Checker-Version: SpamAssassin 3.3.1 (2010-03-16) on pdx-wl-mail.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-5.2 required=2.0 tests=BAYES_00, MAILING_LIST_MULTI, RCVD_IN_DNSWL_MED autolearn=ham version=3.3.1 Received: from gabe.freedesktop.org (gabe.freedesktop.org [131.252.210.177]) (using TLSv1.2 with cipher DHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.wl.linuxfoundation.org (Postfix) with ESMTPS id 31E5929635 for ; Fri, 29 Jun 2018 17:26:49 +0000 (UTC) Received: from gabe.freedesktop.org (localhost [127.0.0.1]) by gabe.freedesktop.org (Postfix) with ESMTP id 69A256F11B; Fri, 29 Jun 2018 17:26:45 +0000 (UTC) X-Original-To: dri-devel@lists.freedesktop.org Delivered-To: dri-devel@lists.freedesktop.org Received: from fllv0016.ext.ti.com (fllv0016.ext.ti.com [198.47.19.142]) by gabe.freedesktop.org (Postfix) with ESMTPS id 52F636F119 for ; Fri, 29 Jun 2018 17:26:44 +0000 (UTC) Received: from dflxv15.itg.ti.com ([128.247.5.124]) by fllv0016.ext.ti.com (8.15.2/8.15.2) with ESMTP id w5TH2sZZ041833; Fri, 29 Jun 2018 12:02:54 -0500 Received: from DLEE108.ent.ti.com (dlee108.ent.ti.com [157.170.170.38]) by dflxv15.itg.ti.com (8.14.3/8.13.8) with ESMTP id w5TH2sY9006297; Fri, 29 Jun 2018 12:02:54 -0500 Received: from DLEE104.ent.ti.com (157.170.170.34) by DLEE108.ent.ti.com (157.170.170.38) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1466.3; Fri, 29 Jun 2018 12:02:54 -0500 Received: from dflp33.itg.ti.com (10.64.6.16) by DLEE104.ent.ti.com (157.170.170.34) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_RSA_WITH_AES_256_CBC_SHA) id 15.1.1466.3 via Frontend Transport; Fri, 29 Jun 2018 12:02:53 -0500 Received: from uda0869644a.dhcp.ti.com (ileax41-snat.itg.ti.com [10.172.224.153]) by dflp33.itg.ti.com (8.14.3/8.13.8) with ESMTP id w5TH2q8V002439; Fri, 29 Jun 2018 12:02:53 -0500 From: Benoit Parrot To: , Laurent Pinchart , Rob Clark , Daniel Vetter Subject: [RFC 1/3] drm/omap: Add ability to check if requested plane modes can be supported Date: Fri, 29 Jun 2018 12:02:47 -0500 Message-ID: <20180629170249.21921-2-bparrot@ti.com> X-Mailer: git-send-email 2.9.0 In-Reply-To: <20180629170249.21921-1-bparrot@ti.com> References: <20180629170249.21921-1-bparrot@ti.com> MIME-Version: 1.0 X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 X-BeenThere: dri-devel@lists.freedesktop.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: Direct Rendering Infrastructure - Development List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Peter Ujfalusi , Tomi Valkeinen , Jyri Sarha Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" X-Virus-Scanned: ClamAV using ClamSMTP We currently assumed that an overlay has the same width and height as the overlay manager. This assumption is incorrect. On some variant the overlay manager is twice the width that the overlay can handle. We need to add the appropriate data per variant as well as export a helper function to retrieve the data so check can be made dynamically. We currently add such a check in the dispc_ovl_setup() which will return an error along with a WARN in case the required width exceed the overlay's ability. Signed-off-by: Benoit Parrot --- drivers/gpu/drm/omapdrm/dss/dispc.c | 29 +++++++++++++++++++++++++++++ drivers/gpu/drm/omapdrm/dss/omapdss.h | 2 ++ 2 files changed, 31 insertions(+) diff --git a/drivers/gpu/drm/omapdrm/dss/dispc.c b/drivers/gpu/drm/omapdrm/dss/dispc.c index cfdcc3681494..1b7a6ef7897f 100644 --- a/drivers/gpu/drm/omapdrm/dss/dispc.c +++ b/drivers/gpu/drm/omapdrm/dss/dispc.c @@ -103,6 +103,8 @@ struct dispc_features { u8 mgr_height_start; u16 mgr_width_max; u16 mgr_height_max; + u16 ovl_width_max; + u16 ovl_height_max; unsigned long max_lcd_pclk; unsigned long max_tv_pclk; unsigned int max_downscale; @@ -2605,6 +2607,13 @@ static int dispc_ovl_calc_scaling(struct dispc_device *dispc, return 0; } +static void dispc_ovl_get_max_size(struct dispc_device *dispc, + u16 *width, u16 *height) +{ + *width = dispc->feat->ovl_width_max; + *height = dispc->feat->ovl_height_max; +} + static int dispc_ovl_setup_common(struct dispc_device *dispc, enum omap_plane_id plane, enum omap_overlay_caps caps, @@ -2648,6 +2657,11 @@ static int dispc_ovl_setup_common(struct dispc_device *dispc, out_width = out_width == 0 ? width : out_width; out_height = out_height == 0 ? height : out_height; + if (WARN(out_width > dispc->feat->ovl_width_max, + "Requested OVL width (%d) is larger than can be supported (%d).\n", + out_width, dispc->feat->ovl_width_max)) + return -EINVAL; + if (plane != OMAP_DSS_WB) { if (ilace && height == out_height) fieldmode = true; @@ -4262,6 +4276,8 @@ static const struct dispc_features omap24xx_dispc_feats = { .mgr_height_start = 26, .mgr_width_max = 2048, .mgr_height_max = 2048, + .ovl_width_max = 2048, + .ovl_height_max = 2048, .max_lcd_pclk = 66500000, .max_downscale = 2, /* @@ -4299,6 +4315,8 @@ static const struct dispc_features omap34xx_rev1_0_dispc_feats = { .mgr_height_start = 26, .mgr_width_max = 2048, .mgr_height_max = 2048, + .ovl_width_max = 2048, + .ovl_height_max = 2048, .max_lcd_pclk = 173000000, .max_tv_pclk = 59000000, .max_downscale = 4, @@ -4333,6 +4351,8 @@ static const struct dispc_features omap34xx_rev3_0_dispc_feats = { .mgr_height_start = 26, .mgr_width_max = 2048, .mgr_height_max = 2048, + .ovl_width_max = 2048, + .ovl_height_max = 2048, .max_lcd_pclk = 173000000, .max_tv_pclk = 59000000, .max_downscale = 4, @@ -4367,6 +4387,8 @@ static const struct dispc_features omap36xx_dispc_feats = { .mgr_height_start = 26, .mgr_width_max = 2048, .mgr_height_max = 2048, + .ovl_width_max = 2048, + .ovl_height_max = 2048, .max_lcd_pclk = 173000000, .max_tv_pclk = 59000000, .max_downscale = 4, @@ -4401,6 +4423,8 @@ static const struct dispc_features am43xx_dispc_feats = { .mgr_height_start = 26, .mgr_width_max = 2048, .mgr_height_max = 2048, + .ovl_width_max = 2048, + .ovl_height_max = 2048, .max_lcd_pclk = 173000000, .max_tv_pclk = 59000000, .max_downscale = 4, @@ -4435,6 +4459,8 @@ static const struct dispc_features omap44xx_dispc_feats = { .mgr_height_start = 26, .mgr_width_max = 2048, .mgr_height_max = 2048, + .ovl_width_max = 2048, + .ovl_height_max = 2048, .max_lcd_pclk = 170000000, .max_tv_pclk = 185625000, .max_downscale = 4, @@ -4474,6 +4500,8 @@ static const struct dispc_features omap54xx_dispc_feats = { .mgr_height_start = 27, .mgr_width_max = 4096, .mgr_height_max = 4096, + .ovl_width_max = 2048, + .ovl_height_max = 4096, .max_lcd_pclk = 170000000, .max_tv_pclk = 186000000, .max_downscale = 4, @@ -4749,6 +4777,7 @@ static const struct dispc_ops dispc_ops = { .ovl_enable = dispc_ovl_enable, .ovl_setup = dispc_ovl_setup, .ovl_get_color_modes = dispc_ovl_get_color_modes, + .ovl_get_max_size = dispc_ovl_get_max_size, .wb_get_framedone_irq = dispc_wb_get_framedone_irq, .wb_setup = dispc_wb_setup, diff --git a/drivers/gpu/drm/omapdrm/dss/omapdss.h b/drivers/gpu/drm/omapdrm/dss/omapdss.h index 14d74adb13fb..3f264759eecb 100644 --- a/drivers/gpu/drm/omapdrm/dss/omapdss.h +++ b/drivers/gpu/drm/omapdrm/dss/omapdss.h @@ -743,6 +743,8 @@ struct dispc_ops { const u32 *(*ovl_get_color_modes)(struct dispc_device *dispc, enum omap_plane_id plane); + void (*ovl_get_max_size)(struct dispc_device *dispc, + u16 *width, u16 *height); u32 (*wb_get_framedone_irq)(struct dispc_device *dispc); int (*wb_setup)(struct dispc_device *dispc,